M68AF127BL55NK1 데이터 시트보기 (PDF) - STMicroelectronics

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M68AF127BL55NK1

1Mbit (128K x8), 5V Asynchronous SRAM

STMicroelectronics 

M68AF127B

SUMMARY DESCRIPTION

The M68AF127B is a 1Mbit (1,048,576 bit) CMOS

SRAM, organized as 131,072 words by 8 bits. The

device features fully static operation requiring no

external clocks or timing strobes, with equal ad-

dress access and cycle times. It requires a single

4.5 to 5.5V supply.

This device has an automatic power-down feature,

reducing the power consumption by over 99%

when deselected.

The M68AF127B is available in SO32, PDIP32,

TSOP32 (8x13.4mm) and TSOP32 (8x20mm)

packages.

Figure 2. Logic Diagram

VCC

17

A0-A16

8

DQ0-DQ7

W

E1

M68AF127B

E2

G

Table 1. Signal Names

A0-A16

Address Inputs

DQ0-DQ7 Data Input/Output

E1

Chip Enable

E2

Chip Enable

G

Output Enable

W

Write Enable

VCC

Supply Voltage

VSS

Ground

VSS

AI05472B

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