HM628128DLR-7SL 데이터 시트보기 (PDF) - Hitachi -> Renesas Electronics

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HM628128DLR-7SL

1 M SRAM (128-kword × 8-bit)

Hitachi -> Renesas Electronics 

HM628128D Series

Block Diagram

LSB

A12

A7

A6

A5

A4

A3

A2

A1

A0

A10

MSB

I/O0

I/O7

CS1

CS2

WE

OE

VCC

VSS

•

•

•

Row

•

decoder •

Memory matrix

512 x 2,048

•

Column I/O

•

•

•

Input

data

control

Column decoder

LSB A14 A16 A15 A13 A8 A9 A11 MSB

••

Timing pulse generator

Read/Write control

4

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