TQ6124 데이터 시트보기 (PDF) - TriQuint Semiconductor
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TQ6124 Datasheet PDF : 9 Pages
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TQ6124
Table 5. Signal-Pin Descriptions
Signal
DGND
AGND
D0 thru D13
VO, NVO
CLK, NCLK
IREF
VSENSE
VREF
VSS
VAA
Mid_trim
LSB_trim
ECLref
Pin(s)
6, 7, 8, 28, 29, 37, 40
13, 15, 18, 19
30, 31, 32, 35, 36, 38, 39,
41, 42, 43, 2, 3, 4, 5
17, 16
9, 10
14
20
21
1, 11, 12, 33, 34, 44
22, 23, 24
25
26
27
Description
Ground connection for digital circuitry.
Ground connection for analog circuitry.
Data inputs. D0 is the least significant bit. ECL levels.
True and complementary analog outputs.
True and complementary clock inputs. ECL levels.
Connect to AGND. Source of dummy currents in the switch array.
Sense Output.
Reference Input.
Digital negative power supply.
Analog negative power supply.
Trim terminal for mid range bits.
Trim terminal for LSB range bits.
Optional ECL reference level adjustment. Thevinin equivalent is 1.3V
nominally into 400 ohms. Equivalent voltage tracks with digital supply.
Typical Performance Data
The graph in Figure 7 shows representative
performance data of spurious free dynamic range
(SFDR) vs. output frequency performance measured
from TQ6124 devices.
Data was collected at room temperature; note,
however, that SFDR is not strongly dependendent on
temperature. Optimum performance is obtained by
utilizing as high a clock rate as practical.
Figure 7. SFDR vs. Output Frequency
–65
–60
–55
–50
SFDR
–45
–40
–35
–30
0
50 100 150 200 250 300 350 400 450 500
FOUT
For additional information and latest specifications, see our website: www.triquint.com
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