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전자부품 반도체 검색엔진( 무료 PDF 다운로드 ) - 데이터시트뱅크

PI74ALVC162835FD 데이터 시트보기 (PDF) - Pericom Semiconductor

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PI74ALVC162835FD
Pericom-Semiconductor
Pericom Semiconductor Pericom-Semiconductor
PI74ALVC162835FD Datasheet PDF : 5 Pages
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PI74ALVC162835FD 111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222
18-Bit Universal Bus Driver
with 3-State Outputs
Product Features
• PI74ALVC162835FD is designed for low voltage operation,
VCC = 2.3V to 3.6V
• Data inputs have clamp diodes to VCC
• Outputs have equivalent 26series resistors
• Supports PC133 Registered DIMM
• Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
• Industrial operation at –40°C to +85°C
• Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 173 mil wide plastic TVSOP (K6)
– 56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor’s PI74ALVC series of logic circuits
are produced using the Company’s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The 18-bit PI74ALVC162835FD universal bus driver is designed
for 2.3V to 3.6V VCC operation.
Data flow from A to Y is controlled by Output Enable (OE).
The device operates in the transparent mode when LE is HIGH. The
A data is latched if CLK is held at a high or low logic level. If LE
is LOW, the A-bus is stored in the latch/flip-flop on the low-to-high
transition of CLK. When OE is HIGH, the outputs are in the high-
impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Logic Block Diagram
OE 27
CLK 30
28
LE
A1 54
1D
C1
CLK
3 Y1
TO 17 OTHER CHANNELS
1
PS8474 04/25/00

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