HFA3524 데이터 시트보기 (PDF) - Intersil
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HFA3524 Datasheet PDF : 15 Pages
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HFA3524
Functional Description
The simplified block diagram in Figure 14 shows the 22-bit
data register, two 15-bit R Counters and the 15-bit and 18-bit
N Counters (intermediate latches are not shown). The data
stream is clocked (on the rising edge of Clock) into the DATA
input, MSB first. The last two bits are the Control Bus. The
DATA is transferred into the counters as follows:
fIN IF
IF
PRESCALER
15-BIT IF
N COUNTER
OSCIN
OSC
fIN RF
RF
PRESCALER
15-BIT IF
R COUNTER
15-BIT RF
R COUNTER
18-BIT RF
N COUNTER
CONTROL BITS
C1
C2
0
0
0
1
1
0
1
1
DATA LOCATION
IR R Counter
RF R Counter
IF N Counter
RF N Counter
PHASE
COMP
CHARGE
PUMP
DO IF
IF
LD
f OUT
LOCK
DETECT
FO/LD
FASTLOCK
RF
MUX
LD
PHASE
COMP
CHARGE
PUMP
DO RF
CLOCK
DATA
LE
22-BIT DATA
REGISTER
FIGURE 14. SIMPLIFIED BLOCK DIAGRAM
Programmable Reference Dividers (IF and RF R Counters)
If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22-bit shift register into a latch which sets the
15-bit R Counter. Serial data format is shown below.
LSB
↓
MSB
↓
C1 C2 R R R R R R R R R R R R R R R R R R R R
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
(Control bits)
Divide ratio of the reference divider, R
Program Modes
15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
DIVIDE
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
RATIO
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
3
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
32767
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
NOTES:
8. Divide ratios less than 3 are prohibited.
9. Divide ratio: 3 to 32767.
10. R1 to R15: These bits select the divide ratio of the programmable reference divider.
11. Data is shifted in MSB first.
9
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