MIC705MY(2014) 데이터 시트보기 (PDF) - Micrel

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MIC705MY
(Rev.:2014)

µP Supervisory Circuit

Micrel 

Micrel, Inc.

MIC705/706/707/708

Pin Description (Continued)

Pin Number

MIC706

7

8

N/A

Pin Number

MIC708

7

N/A

8

Pin Name Pin Name

/RESET

/WDO

RESET

/RESET is asserted if either VCC goes below the reset threshold voltage or by low

signal on the manual reset input (/MR). /RESET remains asserted for one reset

timeout period (200ms) after VCC exceeds the reset threshold voltage or after the

manual reset pin transition from low to high. The watchdog timer will not assert

/RESET unless /WDO is connected to /MR.

Output for the watchdog timer. The watchdog timer resets itself with each transition

to the watchdog input. If the WDI pin is held high or low for longer than the

watchdog timeout period, /WDO is forced low. /WDO will also be forced low if VCC

is below the reset threshold voltage and will remain low until VCC returns to a valid

level.

RESET is the compliment of /RESET and is asserted if either VCC goes below the

reset threshold voltage or by a low signal on the manual reset input (/MR). RESET

is suitable for microprocessor systems that use active high reset.

September 15, 2014

3

Revision 2.1

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