MSC23S2640E 데이터 시트보기 (PDF) - Oki Electric Industry
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MSC23S2640E Datasheet PDF : 11 Pages
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MSC23S2640E-8BS8 (98.08.19)
SERIAL PRESENCE DETECT
Byte
No.
0
SPD
Hex Value
80
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
64-71
72
08
04
0B
09
01
40
00
01
80
60
00
80
08
00
01
8F
02
06
01
01
00
06
C0
A0
00
00
14
14
14
30
04
20
10
20
10
00-00
12
2E
41,45,20,20,20,20,20,20
01 / 06
73-90
91, 92
93-125
126
127
128-255
43,32,33,53,32,36,34,30,45,
2D,38,42,53,38,20,20,20,20
20, 20
00-00
64
A5
FF-FF
Remark
Notes
Defines the number of bytes written into
SPD memory
128 byte
Total number of bytes of SPD memory 256 byte
Fundamental memory type
Number of rows
Number of columns
SDRAM
11 rows
9 columns
Number of module banks
1 bank
Data width of this assembly
... Data width continuation
Voltage interface level
64 bits
0
LVTTL
Cycle time (CL=3)
Access time from CLK (CL=3)
DIMM configuration type
Refresh rate / type
CL=3 tCC=8ns
CL=3 tAC3=6ns
Non Parity
Normal / Self
Primary SDRAM width
Error checking SDRAM width
Minimum CLK delay
Burst lengths supported
x8
tCCD: 1 CLK
1, 2, 4, 8, F
Number of banks on each SDRAM
/CAS latency
/CS latency
2 banks
2, 3
0
/WE latency
SDRAM module attributes
SDRAM device attributes : General
Cycle time (CL=2)
Access time from CLK (CL=2)
Cycle time (CL=1)
Access time from CLK (CL=1)
0
CL=2 tCC2=12ns
CL=2 tAC2=10ns
Not support
Not support
Minimum ROW pulse width
/RAS to /RAS bank delay
/RAS to /CAS delay
Minimum /RAS precharge time
Density of each bank on module
Command and address signal input setup time
Command and address signal input hold time
Data signal input setup time
tRP=20ns
tRRD=20ns
tRCD=20ns
tRAS=48ns
16MB
2ns
1ns
2ns
Data signal input hold time
SPD data revision code
Checksum for byte 0-62
Manufacturer’s JEDEC ID code
1ns
R.F.U
1.2
Manufacturing location
Manufacturer’s part number
C23S2640E-8BS8
Revision code
R.F.U
Intel specification frequency
Intel specification /CAS latency
Unused storage locations
100MHz
CL=3
Page 4/11
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