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MT28S4M16LCTG-10

SYNCFLASH® MEMORY

Micron Technology 

SDRAM INTERFACE

FUNCTIONAL DESCRIPTION

In general, the 64Mb SyncFlash memory (1 Meg x 16

x 4 banks) is configured as a quad-bank, nonvolatile

SDRAM that operates at 3.3V and includes a synchro-

nous interface (all signals are registered on the positive

edge of the clock signal, CLK). Each of the x16’s

16,777,216-bit banks is organized as 4,096 rows by 256

columns by 16 bits.

Read accesses to the SyncFlash memory are burst

oriented; accesses start at a selected location and con-

tinue for a programmed number of locations in a pro-

grammed sequence. Accesses begin with the registra-

tion of an ACTIVE command, followed by a READ com-

mand. The address bits registered coincident with the

ACTIVE command are used to select the bank and row

to be accessed (BA0 and BA1 select the bank, A0–A11

select the row). The address bits registered coincident

with the READ command are used to select the starting

column location for the burst access (BA0 and BA1 se-

lect the bank, A0–A7 select the column).

Prior to normal operation, the SyncFlash memory

must be initialized. The following sections provide de-

tailed information covering device initialization, regis-

ter definition, command descriptions, and device op-

eration.

Initialization

SyncFlash memory must be powered up and initial-

ized in a predefined manner. Operational procedures

other than those specified may result in undefined

operation. After power is applied to VCC, VCCQ, and VCCP

(simultaneously), and the clock is stable, RP# must be

brought from LOW to HIGH. A 100µs delay is required

after RP# transitions HIGH in order to complete inter-

nal device initialization.

The SyncFlash memory is now in the array read mode

and ready for mode register programming or an ex-

ecutable command. After initial programming of the

nvmode register, the contents are automatically loaded

into the mode register during initialization and the

device will power up in the programmed state.

Register Definition

MODE REGISTER

The mode register is used to define the specific mode

of operation of the SyncFlash memory. This definition

includes the selection of a burst length, a burst type, a

CAS latency, and an operating mode, as shown in Fig-

ure 1. The mode register is programmed via the LOAD

MODE REGISTER command and will retain the stored

information until it is reprogrammed. The contents of

the mode register may be copied into the nvmode reg-

4 MEG x 16

SYNCFLASH MEMORY

ister; the mode register settings automatically load the

mode register during initialization. Details on erase

nvmode register and program nvmode register com-

mand sequences are found in the Command Execu-

tion section of the Flash Memory Functional Descrip-

tion.

Mode register bits M0–M2 specify the burst length,

M3 specifies the burst type (sequential or interleaved),

M4–M6 specify the CAS latency, M7 and M8 specify the

operating mode, M9 specifies the write burst mode in

an SDRAM (M9 = 1 by default), and M10 and M11 are

reserved for future use.

The mode register must be loaded when all banks

are idle, and the controller must wait the specified time

before initiating the subsequent operation. Violating

either of these requirements will result in unspecified

operation.

BURST LENGTH

Read accesses to the SyncFlash memory are burst

oriented, with the burst length being programmable,

as shown in Figure 1. The burst length determines the

maximum number of column locations that can be ac-

cessed for a given READ command. Burst lengths of 1,

2, 4, or 8 locations are available for both sequential and

interleaved burst types, and a full-page burst is avail-

able for the sequential type. The full-page burst is

used in conjunction with the BURST TERMINATE com-

mand to generate arbitrary burst lengths.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may

result.

When a READ command is issued, a block of col-

umns equal to the burst length is effectively selected.

All accesses for that burst take place within this block,

meaning that the burst will wrap within the block if a

boundary is reached. The block is uniquely selected by

A1–A7 when the burst length is set to two, by A2–A7

when the burst length is set to four, and by A3–A7 when

the burst length is set to eight. The remaining (least

significant) address bit(s) are used to select the start-

ing location within the block. Full-page bursts wrap

within the page if the boundary is reached.

BURST TYPE

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to

as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type, and the

starting column address, as shown in Table 1.

4 Meg x 16 SyncFlash

MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01

7

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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