IDT7MP4120S25Z 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT7MP4120S25Z

1M x 32 CMOS STATIC RAM MODULE

Integrated Device Technology 

IDT7MP4120

1M x 32 CMOS STATIC RAM MODULE

TIMING WAVEFORM OF READ CYCLE NO. 1(1)

ADDRESS

OE

CS

DATA OUT

tRC

tAA

tACS

tCLZ (5)

tOE

tOLZ (5)

TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)

tRC

ADDRESS

tAA

tOH

DATAOUT

PREVIOUS DATA VALID

COMMERCIAL TEMPERATURE RANGE

tOH

tOHZ (5)

tCHZ (5)

3019 drw 05

t OH

DATA VALID

3019 drw 06

TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)

CS

DATAOUT

tCLZ (5)

tACS

NOTES:

1. WE is HIGH for Read Cycle.

2. Device is continuously selected. CS = VIL.

3. Address valid prior to or coincident with CS transition LOW.

4. OE = VIL.

5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.

tCHZ (5)

3019 drw 07

7.07

5

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