MMA7455L(2007) 데이터 시트보기 (PDF) - Freescale Semiconductor

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MMA7455L
(Rev.:2007)

±2g/±4g/±8g Three Axis Low-g Digital Output Accelerometer

Freescale Semiconductor 

$17: Interrupt latch reset (Read/Write)

D7

D6

D5

D4

D3

D2

D1

D0

Bit

--

--

--

--

--

--

CLR_INT2 CLR_INT1 Function

0

0

0

0

0

0

0

0

Default

CLR_INT1

1: Clear “INT1” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in “Detection source” register depending on “Detection control” reg-

ister setting.

0: Do not clear “INT1” LDX/LDY/LDZ or PDX/PDY/PDZ bits in “Detection source” register.

CLR_INT2

1: Clear “INT2” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in “Detection source” register depending on “Detection control” reg-

ister setting.

0: Do not clear “INT2” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in “Detection source” register.

EXAMPLE: How to clear both interrupt flags

This example is to show how to reset the interrupt flags

void ClearIntLatch(void)

{

IIC_ByteWrite(INTRST, 0x03);

IIC_ByteWrite(INTRST, 0x00);

}

To clear the interrupts you must first write a logic 1 into both registers and then a logic 0.

$18: Control 1 (Read/Write)

D7

DFBW

0

D6

THOPT

0

D5

ZDA

0

D4

YDA

0

D3

XDA

0

D2

D1

INTREG[1] INTREG[0]

0

0

D0

INTPIN

0

INTPIN

0: INT1 pin is routed to “INT1” register and INT2 pin is routed to “INT2” register.

1: INT2 pin is routed to “INT1” register and INT1 pin is routed to “INT2” register.

Bit

Function

Default

INTREG[1:0]

“INT1” register bit

00

Level Detection

01

Pulse Detection

10

Single pulse detection (*Note)

Note: Assigned to single pulse detection even if double

pulse detection is selected. “Double pulse detection se-

lected” means “Time window for 2nd pulse” is not equal to

zero. When double pulse detection is selected, INT1 reg-

ister bit is not able to be cleared by setting CLR_INT1 bit.

It’s cleared by setting CLR_INT2 bit. In this case, setting

CLR_INT2 clears both INT1 and INT2 register bits and re-

set detecting operation itself.

XDA

1: X axis is disabled for detection.

0: X axis is enabled for detection.

YDA

1: Y axis is disabled for detection.

0: Y axis is enabled for detection.

ZDA

1: Z axis is disabled for detection.

0: Z axis is enabled for detection.

“INT2” register bit

Pulse Detection

Level Detection

Pulse Detection

THOPT (This bit is valid for level detection only, not

valid for pulse detection)

0: Threshold value is absolute only

1: Positive/Negative threshold value is available.

DFBW

0: Digital filter band width is 62.5 Hz

1: Digital filter band width is 125 Hz

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MMA7455L

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