ALC5616 데이터 시트보기 (PDF) - Realtek Semiconductor

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ALC5616

Ultra-Low Power Audio CODEC for Mobile Devices

Realtek Semiconductor 

ALC5616

Datasheet

7.4. Clocking

The system clock of ALC5616 can be selected from MCLK or PLL. MCLK is always provided externally

while the reference clock of PLL can be selected from MCLK, BCLK1. The driver should arrange the

clock of each block and setup each divider.

The Clk_sys_i2s1=256*Fs provides clocks into stereo1 DAC/ADC filter that can be selected from MCLK

or PLL. Refer to Figure 5. Audio SYSCLK

When ALC5616 at master mode, the clock source from MCLK will be divided and be sent to external

device. The ratio of BCLK and LRCK can set by register – MX73.

MCLK

MX80[3]

÷2

MX80[13:12]

(Slave)

MX80[15:14]

MCLK

Inter. Clock

PLL

MX81 & MX82

PLL

MX73[14:12]

DIV_F1 Clk_sys_i2s1(256FS)

Stereo1

DAC/ADC

BCLK1

LRCK1

MX70[15]

BCLK1(Master)

MX70[15]

LRCK1(Master)

LRCK1(Slave)

Master Mode

LRCK/BCLK

Ratio

(64FS)

Clk_sys_i2s1 (256FS)

Figure 5. Audio Clock Tree

I2S Audio CODEC for Mobile Devices

13

Rev. 0.1

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