AD74111YRU 데이터 시트보기 (PDF) - Analog Devices
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AD74111YRU Datasheet PDF : 20 Pages
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ADC
MODULATOR
64 ؋ fS
5th ORDER
8 ؋ fS
COMB FILTER
4 ؋ fS
HALF-BAND
COMB
2 ؋ fS
COMPENSATION
Figure 5a. ADC Filter Section
AD74111
fS
HALF-BAND
ADC
RESULT
LOW GROUP
DELAY OUTPUT
DAC
MODULATOR
128 ؋ fS
16 ؋ ZERO
8 ؋ fS
ORDER HOLD
HALF-BAND
FILTER
4 ؋ fS
ZERO ORDER HOLD 2 ؋ fS
SINC COMPENSATION
FILTER
HALF-BAND– fS
FILTER
Figure 5b. DAC Filter Section
DAC
INPUT
LOW GROUP
DELAY INPUT
ADC, CAPP, and CAPN Pins
The ADC channel requires two external capacitors to act as
charge reservoirs for the switched capacitor inputs of the sigma-
delta modulator. These capacitors isolate the outputs of the PGA
stage from glitches generated by the sigma-delta modulator. The
capacitor also forms a low-pass filter with the output impedance
of the PGA (approximately 124 Ω), which helps to isolate noise
from the modulator engine. The capacitors should be of good
quality, such as NPO or polypropylene film, with values from
100 pF to 1 nF and should be connected to AGND.
Peak Readback
The AD74111 can store the highest ADC value to facilitate level
adjustment of the input signal. Programming the Peak Enable
bit in Control Register E with a 1 will enable ADC Peak Level
Reading. The peak value is stored as a 6-bit number from 0 dB
to –63 dB in 1 dB steps. Reading Control Register F will give the
highest ADC value since the bit was set. The ADC peak register
is automatically cleared after reading.
Decimator Section
The digital decimation filter has a pass-band ripple of 0.2 mdB
and a stop-band attenuation of 120 dB. The filter is an FIR type
with a linear phase response. The group delay at 48 kHz is
910 µs. Output sample rates up to 48 kHz are supported.
Input Signal Swing
The ADC input has an input range of 0.5 V rms/1.414 V p-p
about a bias point equal to VREFCAP. Figure 6 shows a typical
input filter circuit for use with the AD74111.
1.414V p-p
VAGND
؉ 51⍀
VIN
47F 10nF
NPO
Figure 6. Typical Input Circuit
DAC Section
The AD74111 DAC channel has a single-ended, analog output.
The DAC has independent software controllable Mute and Volume
Control functions. Control Register G controls the attenuation
factor for the DAC. This register is 10 bits wide, giving 1024
steps of attenuation. The AD74111 output channel employs a
multibit sigma-delta conversion technique that provides a high
quality output with system filtering implemented on-chip.
Output Signal Swing
The DAC has an output range of 0.5 V rms/1.414 V p-p about
a bias point equal to VREFCAP (see Figure 7).
VOUT
820⍀
VREFCAP
2n2F
NPO
1.414V p-p
Figure 7. Typical Output Circuit
Low Group Delay
It is possible to bypass much of the digital filtering by enabling
the Low Group Delay function in Control Register C. By reduc-
ing the amount of filtering the AD74111 applies to input and
output samples, the time delay between the sampling interval
and when the sample is available is greatly reduced. This can be
of benefit in applications such as telematics, where minimal
time delays are important. When the Low Group Delay function
is enabled, the sample rate becomes IMCLK/128.
Reference
The AD74111 features an on-chip reference whose nominal
value is 1.125 V. A 100 nF ceramic and 10 µF tantalum capacitor
applied at the REFCAP pin are necessary to stabilize the reference.
(See Figure 8.)
10F 0.1F
REFCAP
Figure 8. Reference Decoupling
If required, an external reference can be used as the reference
source of the ADC and DAC sections. This may be desirable in
situations where multiple devices are required to use the same
value of reference or because of a better temperature coefficient
specification. The internal reference can be disabled via Control
Register A and the external reference applied at the REFCAP
pin (see Figure 9). External references should be of a suitable
value such that the voltage swing of the inputs or outputs is not
affected by being too close to the power supply rails and should
be adequately decoupled.
REV. 0
–9–
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