AD5694R 데이터 시트보기 (PDF) - Analog Devices
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AD5694R Datasheet PDF : 32 Pages
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AD5696R/AD5695R/AD5694R
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5696R/AD5695R/AD5694R
Data Sheet
VOUTA 1
GND 2
VDD 3
VOUTC 4
12 A1
11 SCL
10 A0
9 VLOGIC
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PAD MUST BE TIED TO GND.
Figure 3. 16-Lead LFCSP Pin Configuration
VREF 1
VOUTB 2
VOUTA 3
GND 4
VDD 5
VOUTC 6
VOUTD 7
SDA 8
16 RSTSEL
AD5696R/
AD5695R/
AD5694R
15 RESET
14 A1
13 SCL
TOP VIEW
(Not to Scale)
12
A0
11 VLOGIC
10 GAIN
9 LDAC
Figure 4. 16-Lead TSSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
LFCSP TSSOP
Mnemonic
1
3
VOUTA
2
4
GND
3
5
VDD
4
6
5
7
6
8
VOUTC
VOUTD
SDA
7
9
LDAC
8
10
9
11
10
12
11
13
12
14
13
15
GAIN
VLOGIC
A0
SCL
A1
RESET
14
16
15
1
16
2
17
N/A
RSTSEL
VREF
VOUTB
EPAD
Description
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be
decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the
24-bit input shift register. SDA is a bidirectional, open-drain data line that should be pulled to the
supply with an external pull-up resistor.
LDAC can be operated in two modes, asynchronously and synchronously. Pulsing this pin low allows
any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs
to simultaneously update. This pin can also be tied permanently low.
Span Set Pin. When this pin is tied to GND, all four DAC outputs have a span from 0 V to VREF. If this
pin is tied to VDD, all four DACs output a span of 0 V to 2 × VREF.
Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V.
Address Input. Sets the first LSB of the 7-bit slave address.
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 24-bit
input register.
Address Input. Sets the second LSB of the 7-bit slave address.
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC
pulses are ignored. When RESET is activated, the input register and the DAC register are updated
with zero scale or midscale, depending on the state of the RSTSEL pin.
Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to
VDD powers up all four DACs to midscale.
Reference Voltage. The AD5696R/AD5695R/AD5694R have a common reference pin. When using
the internal reference, this is the reference output pin. When using an external reference, this is the
reference input pin. The default for this pin is as a reference output.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Exposed Pad. The exposed pad must be tied to GND.
Rev. 0 | Page 8 of 32
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