AD5694RARUZ(2017) 데이터 시트보기 (PDF) - Analog Devices
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AD5694RARUZ
(Rev.:2017)
(Rev.:2017)
Analog Devices
AD5694RARUZ Datasheet PDF : 29 Pages
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AD5696R/AD5695R/AD5694R
Data Sheet
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V; 1.62 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. 1
Table 4.
Parameter2
t1
t2
t3
t4
t5
t63
t7
t8
t9
t10
t11
t12
t13
tSP5
CB4
Min
2.5
0.6
1.3
0.6
100
0
0.6
0.6
1.3
0
20 + 0.1CB4
20
400
0
Max
0.9
300
300
50
400
Unit
μs
μs
μs
μs
ns
μs
μs
μs
μs
ns
ns
ns
ns
ns
pF
Conditions/Comments
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD,STA, start/repeated start condition hold time
tSU,DAT, data setup time
tHD,DAT, data hold time
tSU,STA, setup time for repeated start
tSU,STO, stop condition setup time
tBUF, bus free time between a stop and a start condition
tR, rise time of SCL and SDA when receiving
tF, fall time of SDA and SCL when transmitting/ receiving
LDAC pulse width
SCL rising edge to LDAC rising edge
Pulse width of suppressed spike
Capacitive load for each bus line
1 See Figure 2.
2 Guaranteed by design and characterization; not production tested.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of SCL’s
falling edge.
4 CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.
5 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns.
START
CONDITION
SDA
SCL
t9
t3
t4
t10
t6
LDAC1
LDAC2
NOTES
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
REPEATED START
CONDITION
t11
t4
t2
t5
t1
t7
t13
t12
Figure 2. 2-Wire Serial Interface Timing Diagram
STOP
CONDITION
t8
t12
Rev. D | Page 6 of 29
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