AD7607 데이터 시트보기 (PDF) - Analog Devices
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AD7607 Datasheet PDF : 32 Pages
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AD7607
Data Sheet
Parameter
t27
t28
t29
Limit at TMIN, TMAX
Min Typ Max
19
24
17
22
24
Unit
ns
ns
ns
ns
ns
Description
Delay from RD falling edge to FRSTDATA low
VDRIVE = 3.3 V to 5.25 V
VDRIVE = 2.3 V to 2.7 V
Delay from 16th SCLK falling edge to FRSTDATA low
VDRIVE = 3.3 V to 5.25 V
VDRIVE = 2.3 V to 2.7 V
Delay from CS rising edge until FRSTDATA three-state enabled
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
2 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <3 LSB performance matching between channel sets.
3 A buffer, which is equivalent to a load of 20 pF on the output pins, is used on the data output pins for these measurements.
Timing Diagrams
CONVST A,
CONVST B
CONVST A,
CONVST B
BUSY
CS
RESET
t5
t1
t7
tRESET
tCYCLE
t3
tCONV
t2
t4
Figure 2. CONVST Timing—Reading After a Conversion
t5
CONVST A,
CONVST B
CONVST A,
CONVST B
tCYCLE
t2
t3
tCONV
t1
BUSY
t6
CS
RESET
t7
tRESET
Figure 3. CONVST Timing—Reading During a Conversion
CS
RD
DATA:
DB[15:0]
FRSTDATA
t8
t10
t11
t13
t14
t15
INVALID
V1
V2
V3
V4
V7
t26
t27
t24
Figure 4. Parallel Mode, Separate CS and RD Pulses
Rev. B | Page 8 of 32
t9
t16
t17
V8
t29
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