AD8155 데이터 시트보기 (PDF) - Analog Devices
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AD8155 Datasheet PDF : 36 Pages
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Lane Disables
By default, the receivers and transmitters enable in an on-demand
fashion according to the state of the SEL[1:0], LB_[A:C], and
BICAST pins or to the state of the equivalent registers in serial
control mode. Register 0x40, Register 0x80, and Register 0xC0
implement per-lane disables for the receivers, and Register 0x48,
Register 0x88, and Register 0xC8 implement per-lane transmit-
ter disables. These disables override the default settings. Each
bit in the register is named for the lane and function it disables.
For example, RXDIS B0 disables the receiver on Lane 0 of Port B
whereas TXDIS C1 disables the Lane 1 transmitter of Port C
(see Table 11).
AD8155
Lane Inversion: P/N Swap
The receiver P/N swap function is a convenience intended to
allow the user to implement the equivalent of a board-level
routing crossover in a much smaller area while eliminating vias
(impedance discontinuities) that compromise the high frequency
integrity of the signal path. Using this feature to correct an
inversion downstream of the receiver may require the user to be
aware of the sign of the data when switching connectivity (the
mux/demux path). The feature is available on a per-lane setting
through Register 0x44, Register 0x84, and Register 0xC4.
Setting the bit true flips the sign sense of the P and N inputs for
the associated lane. The default setting is 0 (no inversion).
Table 11. Per-Lane Disables
Address Port Default Register Name
Bit
0x40
Port A 0x00
RX[A/B/C] disable
7:4
0x80
Port B 0x00
3:2
0xC0
Port C 0x00
1
0
0x48
0x88
0xC8
Port A 0x00
TX[A/B/C] disable
7:4
Port B 0x00
3:2
Port C 0x00
1
0
Table 12. Lane Inversion
Address Port Default Register Name
Bit
0x44
Port A 0x00
RX[A/B/C] P/N swap 7:2
0x84
Port B 0x00
1
0xC4
Port C 0x00
0
Table 13. Port-Level EQ Setting
Address Port Default Register Name
Bit
0x41
Port A 0x00
RX[A/B/C] EQ setting 7:4
0x81
Port B 0x00
3:0
0xC1
Port C 0x00
Bit Name
Reserved
Reserved
RXDIS [A/B/C]1
RXDIS [A/B/C]0
Reserved
Reserved
TXDIS [A/B/C]1
TXDIS [A/B/C]0
Functionality Description
Set to 0
0: RX Port [A/B/C], Lane 1, enabled
1: RX Port [A/B/C], Lane 1, disabled
0: RX Port [A/B/C], Lane 0, enabled
1: RX Port [A/B/C], Lane 0, disabled
Set to 0
0: TX Port [A/B/C], Lane 1, enabled
1: TX Port [A/B/C], Lane 1, disabled
0: TX Port [A/B/C], Lane 0, enabled
1: TX Port [A/B/C], Lane 0, disabled
Bit Name
Reserved
PN[A/B/C]1
PN[A/B/C]0
Functionality Description
Set to 0
0: Lane 1, noninverted
1: Lane 1, inverted
0: Lane 0, noninverted
1: Lane 0, inverted
Bit Name
Reserved
[A/B/C]EQ[3:0]
Functionality Description
Set to 0
Rev. 0 | Page 19 of 36
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