AD7663 데이터 시트보기 (PDF) - Analog Devices
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AD7663 Datasheet PDF : 24 Pages
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AD7663
TIMING SPECIFICATIONS (continued)
Parameter
Symbol Min
Typ
Max
Refer to Figures 17 and 18 (Master Serial Interface Modes)1
CS HIGH to SYNC HI-Z
t25
CS HIGH to Internal SCLK HI-Z
t26
CS HIGH to SDOUT HI-Z
t27
BUSY HIGH in Master Serial Read after Convert
t28
CNVST LOW to SYNC Asserted Delay
t29
(Master Serial Read after Convert)
SYNC Deasserted to BUSY LOW Delay
t30
10
10
10
See Table II
1.25
25
Refer to Figures 19 and 21 (Slave Serial Interface Modes)
External SCLK Setup Time
t31
5
External SCLK Active Edge to SDOUT Delay
t32
3
16
SDIN Setup Time
t33
5
SDIN Hold Time
t34
5
External SCLK Period
t35
25
External SCLK HIGH
t36
10
External SCLK LOW
t37
10
NOTES
1In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwise, the load is 60 pF maximum.
2In Serial Master Read during Convert Mode. See Table II for Master Read after Convert Mode.
Specifications subject to change without notice.
Unit
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
Table II. Serial Clock Timings in Master Read after Convert
DIVSCLK[1]
DIVSCLK[0]
SYNC to SCLK First Edge Delay Minimum
t18
Internal SCLK Period Minimum
t19
Internal SCLK Period Maximum
t19
Internal SCLK HIGH Minimum
t20
Internal SCLK LOW Minimum
t21
SDOUT Valid Setup Time Minimum
t22
SDOUT Valid Hold Time Minimum
t23
SCLK Last Edge to SYNC Delay Minimum
t24
BUSY HIGH Width Maximum
t28
0
0
1
1
0
1
0
1
4
20
20
20
25
50
100
200
40
70
140
280
15
25
50
100
9.5
24
49
99
4.5
22
22
22
2
4
30
90
3
60
140
300
2
2.5
3.5
5.75
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
1.6mA IOL
TO OUTPUT
PIN
CL
60pF*
1.4V
500A IOH
*IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 1. Load Circuit for Digital Interface Timing
0.8V
tDELAY
2V
0.8V
2V
tDELAY
2V
0.8V
Figure 2. Voltage Reference Levels for Timing
–4–
REV. B
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