AD7661 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
일치하는 목록
AD7661 Datasheet PDF : 28 Pages
| |||
AD7661
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted
Parameter
Symbol Min
Typ
Max
Unit
Refer to Figure 33 and Figure 34
Convert Pulse Width
Time between Conversions
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except Master Serial Read after Convert
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
Acquisition Time
RESET Pulse Width
Refer to Figure 35, Figure 36, and Figure 37 (Parallel Interface Modes)
t1
10
t2
10
t3
t4
t5
2
t6
10
t7
t8
8.75
t9
10
ns
µs
35
ns
1.25
µs
ns
ns
1.25
µs
µs
ns
CNVST LOW to DATA Valid Delay
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
Refer to Figure 39 and Figure 40 (Master Serial Interface Modes)1
t10
t11
12
t12
t13
5
1.25
µs
ns
45
ns
15
ns
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay1
CS LOW to SDOUT Delay
CNVST LOW to SYNC Delay
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period2
Internal SCLK HIGH2
Internal SCLK LOW2
SDOUT Valid Setup Time2
SDOUT Valid Hold Time2
SCLK Last Edge to SYNC Delay2
CS HIGH to SYNC HI-Z
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert2
CNVST LOW to SYNC Asserted Delay
SYNC Deasserted to BUSY LOW Delay
Refer to Figure 41 and Figure 42 (Slave Serial Interface Modes)1
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
t14
10
ns
t15
10
ns
t16
10
ns
t17
525
ns
t18
3
ns
t19
25
40
ns
t20
12
ns
t21
7
ns
t22
4
ns
t23
2
ns
t24
3
ns
t25
10
ns
t26
10
ns
t27
10
ns
t28
See Table 4
t29
1.25
µs
t30
25
ns
t31
5
t32
3
t33
5
t34
5
t35
25
t36
10
t37
10
ns
18
ns
ns
ns
ns
ns
ns
1In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
2In serial master read during convert mode. See Table 4 for serial master read after convert mode.
Rev. 0 | Page 5 of 28
Share Link: 