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XRT83SL38

OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

Exar Corporation 

XRT83SL38

OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.1.0

TABLE OF CONTENTS

GENERAL DESCRIPTION .................................................................................................. 1

APPLICATIONS .............................................................................................................................................. 1

Figure 1. Block Diagram of the XRT83SL38 T1/E1/J1 LIU (Host Mode) ........................................ 1

Figure 2. Block Diagram of the XRT83SL38 T1/E1/J1 LIU (Hardware Mode) ............................... 2

FEATURES ................................................................................................................................................... 2

ORDERING INFORMATION ............................................................................................................... 3

Figure 3. Pin Out of the XRT83SL38 ................................................................................................ 3

TABLE OF CONTENTS ....................................................................................................... I

PIN DESCRIPTION BY FUNCTION .................................................................................... 5

RECEIVE SECTIONS ...................................................................................................................................... 5

TRANSMITTER SECTIONS .............................................................................................................................. 7

MICROPROCESSOR INTERFACE ................................................................................................................... 11

JITTER ATTENUATOR .................................................................................................................................. 14

CLOCK SYNTHESIZER ................................................................................................................................. 14

ALARM FUNCTIONS/REDUNDANCY SUPPORT ............................................................................................... 16

POWER AND GROUND ................................................................................................................................ 20

PINS ONLY AVAILABLE IN BGA PACKAGE .......................................................................................... 21

FUNCTIONAL DESCRIPTION .......................................................................................... 22

MASTER CLOCK GENERATOR ..................................................................................................................... 22

Figure 4. Two Input Clock Source .................................................................................................. 22

Figure 5. One Input Clock Source .................................................................................................. 22

RECEIVER ......................................................................................................................... 23

RECEIVER INPUT ........................................................................................................................................ 23

TABLE 1: MASTER CLOCK GENERATOR ............................................................................................... 23

RECEIVE MONITOR MODE ........................................................................................................................... 24

RECEIVER LOSS OF SIGNAL (RLOS) ........................................................................................................... 24

Figure 6. Simplified Diagram of -15dB T1/E1 Short Haul Mode and RLOS Condition .............. 24

RECEIVE HDB3/B8ZS DECODER ............................................................................................................... 25

RECOVERED CLOCK (RCLK) SAMPLING EDGE ............................................................................................ 25

Figure 7. Simplified Diagram of -29dB T1/E1 Gain Mode and RLOS Condition ......................... 25

Figure 8. Receive Clock and Output Data Timing ........................................................................ 25

JITTER ATTENUATOR .................................................................................................................................. 26

GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH) ................................................................ 26

TABLE 2: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS ........................................ 26

ARBITRARY PULSE GENERATOR FOR T1 AND E1 .......................................................................................... 27

TRANSMITTER ................................................................................................................. 27

DIGITAL DATA FORMAT ............................................................................................................................... 27

TRANSMIT CLOCK (TCLK) SAMPLING EDGE ................................................................................................ 27

Figure 9. Arbitrary Pulse Segment Assignment ........................................................................... 27

TRANSMIT HDB3/B8ZS ENCODER .............................................................................................................. 28

Figure 10. Transmit Clock and Input Data Timing ........................................................................ 28

TABLE 3: EXAMPLES OF HDB3 ENCODING .......................................................................................... 28

TABLE 4: EXAMPLES OF B8ZS ENCODING ........................................................................................... 28

DRIVER FAILURE MONITOR (DMO) ............................................................................................................. 29

TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT ...................................................................... 29

TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS ........................... 29

TRANSMIT AND RECEIVE TERMINATIONS .................................................................. 30

RECEIVER (CHANNELS 0 - 7) ................................................................................................................... 30

Internal Receive Termination Mode ................................................................................................................. 30

TABLE 6: RECEIVE TERMINATION CONTROL ......................................................................................... 30

Figure 11. Simplified Diagram for the Internal Receive and Transmit Termination Mode ........ 31

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