XRT83SL38 데이터 시트보기 (PDF) - Exar Corporation
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XRT83SL38 Datasheet PDF : 89 Pages
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XRT83SL38
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.1.0
PRELIMINARY
FIGURE 2. BLOCK DIAGRAM OF THE XRT83SL38 T1/E1/J1 LIU (HARDWARE MODE)
MCLKE1
MCLKT1
CLKSEL[2:0]
TPOS_n/TDATA_n
TNEG_n/CODES_n
TCLK_n
RCLK_n
RNEG_n/LCV_n
RPOS_n/RDATA_n
RLOS_n
HW/HOST
GAUGE
JASEL1
JASEL0
RXTSEL
TXTSEL
TERSELR
XRES0
RXRES1
MASTER CLOCK SYNTHESIZER
One of Eight Channels, CHANNEL_n - (n=0 : 7)
QRSS
PATTERN
GENERATOR
HDB3/
B8ZS
ENCODER
TX/RX JITTER
ATTENUATOR
TIMING
CONTROL
DFM
DRIVE
MONITOR
TX FILTER
& PULSE
SHAPER
LINE
DRIVER
QRSS ENABLE
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
REMOTE
LOOPBACK
DIGITAL
LOOPBACK
LOOPBACK
ENABLE
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
LBO[3:0]
PEAK
DETECTOR
& SLICER
NLCD ENABLE
LOS
DETECTOR
AIS
DETECTOR
EQUALIZER
CONTROL
LOCAL
ANALOG
LOOPBACK
RX
EQUALIZER
TEST
HARWARE CONTROL
MCLKOUT
TAOS_n
DMO_n
TTIP_n
TRING_n
TXON_n
RTIP_n
RRING_n
LOOP1_n
LOOP0_n
ICT
RESET
TRATIO
SR/DR
EQC[4:0]
TCLKE
RCLKE
RXMUTE
ATAOS
FEATURES
• Fully integrated eight channel short-haul transceiv-
ers for E1,T1 or J1 applications
• Programable Transmit Pulse Shaper for E1,T1 or J1
short-haul interfaces
• Five fixed transmit pulse settings for T1 short-haul
applications plus a fully programmable waveform
generator for transmit output pulse shaping avail-
able for both T1 and E1 modes
• Selectable receiver sensitivity from 0 to 36dB cable
loss
• Receive monitor mode handles 0 to 29dB resistive
attenuation along with 0 to 6dB of cable attenuation
for E1 and 0 to 3dB of cable attenuation for T1
modes
• Supports 75Ω and 120Ω (E1), 100Ω (T1) and 110Ω
(J1) applications
• Internal and/or external impedance matching for
75Ω, 100Ω, 110Ω and 120Ω
• Tri-State transmit output and receive input capabil-
ity for redundancy applications
• Provides High Impedance for Tx and Rx during
power off
• Transmit return loss meets or exceeds ETSI 300-
166 standard
• On-chip digital clock recovery circuit for high input
jitter tolerance
• Crystal-less digital jitter attenuator with 32-bit or 64-
bit FIFO selectable either in transmit or receive path
• On-chip frequency multiplier generates T1 or E1
Master clocks from variety of external clock sources
• High receiver interference immunity
• On-chip transmit short-circuit protection and limit-
ing, and driver fail monitor output (DMO)
• Receive loss of signal (RLOS) output
• On-chip HDB3/B8ZS/AMI encoder/decoder func-
tions
• QRSS pattern generator and detection for testing
and monitoring
• Error and Bipolar Violation Insertion and Detection
• Receiver Line Attenuation Indication Output in 1dB
steps
• Network Loop-Code Detection for automatic Loop-
Back Activation/Deactivation
• Transmit All Ones (TAOS) and In-Band Network
Loop Up and Down code generators
• Supports Local Analog, Remote, Digital and Dual
Loop-Back Modes
• Meets or exceeds T1 and E1 short-haul network
access specifications in ITU G.703, G.775, G.736
2
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