XRT83SL38(2007) 데이터 시트보기 (PDF) - Exar Corporation

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XRT83SL38
(Rev.:2007)

OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER

Exar Corporation 

XRT83SL38

OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2

Figure 12. Simplified Diagram for E1 in External Termination Mode (RXTSEL= 0) ................... 34

TRANSMITTER (CHANNELS 0 - 7) ............................................................................................................ 34

Transmit Termination Mode .................................................................................................................................. 34

TABLE 8: TRANSMIT TERMINATION CONTROL ....................................................................................... 34

TABLE 9: TERMINATION SELECT CONTROL ........................................................................................... 34

External Transmit Termination Mode ................................................................................................................... 34

TABLE 10: TRANSMIT TERMINATION CONTROL ..................................................................................... 35

TABLE 11: TRANSMIT TERMINATIONS ................................................................................................... 35

REDUNDANCY APPLICATIONS ............................................................................................................. 35

TYPICAL REDUNDANCY SCHEMES ..................................................................................................... 36

Figure 13. Simplified Block Diagram of the Transmit Section for 1:1 & 1+1 Redundancy ....... 37

Figure 14. Simplified Block Diagram - Receive Section for 1:1 and 1+1 Redundancy .............. 37

Figure 15. Simplified Block Diagram - Transmit Section for N+1 Redundancy ......................... 38

Figure 16. Simplified Block Diagram - Receive Section for N+1 Redundancy ........................... 39

PATTERN TRANSMIT AND DETECT FUNCTION ............................................................................................... 40

TABLE 12: PATTERN TRANSMISSION CONTROL ...................................................................................... 40

TRANSMIT ALL ONES (TAOS) ..................................................................................................................... 40

NETWORK LOOP CODE DETECTION AND TRANSMISSION ............................................................................... 40

TABLE 13: LOOP-CODE DETECTION CONTROL ..................................................................................... 40

TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS) ......................................................... 41

LOOP-BACK MODES .................................................................................................................................... 42

TABLE 14: LOOP-BACK CONTROL IN HARDWARE MODE ........................................................................ 42

TABLE 15: LOOP-BACK CONTROL IN HOST MODE .................................................................................. 42

LOCAL ANALOG LOOP-BACK (ALOOP) ........................................................................................................ 43

Figure 17. Local Analog Loop-back signal flow ............................................................................ 43

REMOTE LOOP-BACK (RLOOP) .................................................................................................................. 43

Figure 18. Remote Loop-back mode with jitter attenuator selected in receive path ................. 43

Figure 19. Remote Loop-back mode with jitter attenuator selected in Transmit path .............. 44

DIGITAL LOOP-BACK (DLOOP) ................................................................................................................... 44

Figure 20. Digital Loop-back mode with jitter attenuator selected in Transmit path ................ 44

DUAL LOOP-BACK ...................................................................................................................................... 45

Figure 21. Signal flow in Dual loop-back mode ............................................................................. 45

MICROPROCESSOR PARALLEL INTERFACE .............................................................. 46

TABLE 16: MICROPROCESSOR INTERFACE SIGNAL DESCRIPTION ........................................................... 46

MICROPROCESSOR REGISTER TABLES ........................................................................................................ 47

TABLE 17: MICROPROCESSOR REGISTER ADDRESS ............................................................................. 47

TABLE 18: MICROPROCESSOR REGISTER BIT DESCRIPTION .................................................................. 47

MICROPROCESSOR REGISTER DESCRIPTIONS .............................................................................................. 51

TABLE 19: MICROPROCESSOR REGISTER #0, BIT DESCRIPTION ............................................................ 51

TABLE 20: MICROPROCESSOR REGISTER #1, BIT DESCRIPTION ............................................................ 52

TABLE 21: MICROPROCESSOR REGISTER #2, BIT DESCRIPTION ............................................................ 54

TABLE 22: MICROPROCESSOR REGISTER #3, BIT DESCRIPTION ............................................................ 56

TABLE 23: MICROPROCESSOR REGISTER #4, BIT DESCRIPTION ............................................................ 58

TABLE 24: MICROPROCESSOR REGISTER #5, BIT DESCRIPTION ............................................................ 59

TABLE 25: MICROPROCESSOR REGISTER #6, BIT DESCRIPTION ............................................................ 61

TABLE 26: MICROPROCESSOR REGISTER #7, BIT DESCRIPTION ............................................................ 62

TABLE 27: MICROPROCESSOR REGISTER #8, BIT DESCRIPTION ............................................................ 63

TABLE 28: MICROPROCESSOR REGISTER #9, BIT DESCRIPTION ............................................................ 63

TABLE 29: MICROPROCESSOR REGISTER #10, BIT DESCRIPTION .......................................................... 64

TABLE 30: MICROPROCESSOR REGISTER #11, BIT DESCRIPTION .......................................................... 64

TABLE 31: MICROPROCESSOR REGISTER #12, BIT DESCRIPTION .......................................................... 65

TABLE 32: MICROPROCESSOR REGISTER #13, BIT DESCRIPTION .......................................................... 65

TABLE 33: MICROPROCESSOR REGISTER #14, BIT DESCRIPTION .......................................................... 66

TABLE 34: MICROPROCESSOR REGISTER #15, BIT DESCRIPTION .......................................................... 66

TABLE 35: MICROPROCESSOR REGISTER #128, BIT DESCRIPTION ........................................................ 67

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