SN260QT 데이터 시트보기 (PDF) - STMicroelectronics
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SN260QT Datasheet PDF : 88 Pages
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Top-level functional description
3
Top-level functional description
Figure 2 shows a detailed block diagram of the SN260.
Figure 2. SN260 block diagram
PA select
TX_ACTIVE
RF_TX_ALT_P,N
RF_P,N
BIAS_R
OSCA
OSCB
VREG_OUT
PA
PA
LNA
Bias
HF OSC
Internal
RC-OSC
Regulator
Chip
manager
SYNTH
DAC
IF
ADC
Encryption acclerator
MAC
+
Baseband
Network
Processor
(XAP2b)
PacketTrace
Network Processor
Peripherals
Serial
Interrupt
Controller Controller
Integrated Flash and RAM
Always
powered
POR
Sleep
timer
Watchdog
IO Controller
SIF
SN260
nRESET
SIF_CLK
SIF_MISO
SIF_MOSI
nSIF_LOAD
The radio receiver is a low-IF, super-heterodyne receiver. It utilizes differential signal paths
to minimize noise interference, and its architecture has been chosen to optimize co-
existence with other devices within the 2.4GHz band (namely, IEEE 802.11g and Bluetooth).
After amplification and mixing, the signal is filtered and combined prior to being sampled by
an ADC.
The digital receiver implements a coherent demodulator to generate a chip stream for the
hardware-based MAC. In addition, the digital receiver contains the analog radio calibration
routines and control of the gain within the receiver path.
The radio transmitter utilizes an efficient architecture in which the data stream directly
modulates the VCO. An integrated PA boosts the output power. The calibration of the TX
path as well as the output power is controlled by digital logic. If the SN260 is to be used with
an external PA, the TX_ACTIVE signal should be used to control the timing of the external
switching logic.
The integrated 4.8GHz VCO and loop filter minimize off-chip circuitry. Only a 24MHz crystal
with its loading capacitors is required to properly establish the PLL reference signal.
The MAC interfaces the data memory to the RX and TX baseband modules. The MAC
provides hardware-based IEEE 802.15.4 packet-level filtering. It supplies an accurate
symbol time base that minimizes the synchronization effort of the software stack and meets
the protocol timing requirements. In addition, it provides timer and synchronization
assistance for the IEEE 802.15.4 CSMA-CA algorithm.
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