SII150A 데이터 시트보기 (PDF) - Unspecified
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SII150A Datasheet PDF : 6 Pages
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Silicon Image, Inc.
Input Timing
IDCK+/IDCK-
D[23:0], DE,
HSYNC,VSYNC,
CTL[3:1]
SiI 150A
TSIDF
50 %
50 %
TSIDR
THIDF
50 %
50 %
THIDR
Figure 3. Input Data Setup/Hold Times to IDCK
SiI/DS-0006-C
DE
VSYNC, HSYNC,
CTL[3:1]
0.8 V
TDDF
0.8 V
DE
VSYNC, HSYNC,
CTL[3:1]
0.8 V
TDDR
Figure 4. VSYNC, HSYNC, and CTL[3:1] Delay Times from DE
0.8 V
THDE
DE
2.0 V
2.0 V
0.8 V
T LDE
Figure 5. DE High/Low Times
0.8 V
Input Pin Description
Pin Name
DIE23-
DIE0
Pin #
See SiI
150A Pin
Diagram
Type
In
DIO23 – See SiI
In
DIO0
150A Pin
Diagram
IDCK
80
In
DE
78
In
HSYNC 76
In
VSYNC 77
In
CTL1
84
In
CTL2
83
In
CTL3
82
In
Description
Even Input Data[23:0] corresponds to 24-bit pixel data for 1-pixel/clock input mode or to the first 24-bit
pixel data for 2-pixels/clock mode.
Input data is synchronized to input data clock (IDCK).
Data can be latched on the rising or the falling edge of IDCK depending on whether EDGE is high or low,
respectively.
Refer to the TFT and DSTN Signal Mapping application notes (SiI-AN-0008-A and SiI-AN-0007-A,
respectively) which tabulate the relationship between the input data to the transmitter and output data from
the receiver.
Input Odd Data[23:0] corresponds to the second 24-bit pixel data for 2-pixels/clock mode.
In 1-pixel/clock mode, these inputs are a don’t care. Recommendation is to tie them low for lower power
consumption.
Input data is synchronized to input data clock (IDCK).
Data can be latched on the rising or the falling edge of IDCK depending on whether EDGE is high or low,
respectively.
Refer to the TFT and DSTN Signal Mapping application notes (SiI-AN-0008-A and SiI-AN-0007-A,
respectively) which tabulate the relationship between the input data to the transmitter and output data from
the receiver.
Input Data Clock. Input data and control signals can be valid either on the falling or the rising edge of
IDCK as selected by the EDGE pin.
Input Data Enable. This signal qualifies the active data area. DE is always required by the transmitter and
must be high during active display time and low during blanking time.
Horizontal Sync input control signal.
Vertical Sync input control signal.
General input control signal 1.
General input control signal 2.
General input control signal 3.
Revision C
4
Subject to Change without Notice
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