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PI74ALVCH16600

18-Bit Universal Bus Transceiver with 3-State Outputs

Pericom Semiconductor 

PI74ALVCH16600

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18-Bit Universal Bus Transceiver

with 3-State Outputs

Product Features

• PI74ALVCH16600 is designed for low voltage operation

• VCC = 2.3V to 3.6V

• Hysteresis on all inputs

• Typical VOLP (Output Ground Bounce)

< 0.8V at VCC = 3.3V, TA = 25°C

• Typical VOHV (Output VOH Undershoot)

< 2.0V at VCC = 3.3V, TA = 25°C

• Bus Hold retains last active bus state during 3-State

eliminating the need for external pullup resistors

• Industrial operation at –40°C to +85°C

• Packages available:

– 56-pin 240 mil wide plastic TSSOP (A)

– 56-pin 300 mil wide plastic SSOP (V)

Logic Block Diagram

Product Description

Pericom Semiconductor’s PI74ALVCH series of logic circuits are

produced in the Company’s advanced 0.5 micron CMOS

technology, achieving industry leading speed.

The PI74ALVCH16600 uses D-type latches and D-type flip-flops

with 3-state outputs to allow data flow in transparent, latched, and

clocked modes.

Data flow in each direction is controlled by Output Enable (OEAB

and OEBA), Latched Enable (LEAB and LEBA), and Clock

(CLKAB and CLKBA) inputs. The clock can be controlled by the

Clock Enable (CLKENAB and CLKENBA) inputs. For A-to-B

data flow, the device operates in the transparent mode when LEAB

is HIGH. When LEAB is LOW, the A data is latched if CLKAB is

held at a high or low logic level. If LEAB is low, the A data is stored

in the latch/flip-flop on the high-to-low transition of CLKAB.

Output enable OEAB is active low. When OEAB is low, the

outputs are active. When OEAB is HIGH, the outputs are in the

high-impedance state.

Data flow for B to A is similar to that of A to B but uses OEBA,

LEBA, CLKBA, and CLKENBA.

To ensure the high-impedance state during power up or power

down, OE should be tied to VCC through a pull-up resistor; the

minimum value of the resistor is determined by the current-sinking

capability of the driver.

The PI74ALVCH16600 has “Bus Hold” which retains the data

input’s last state whenever the data input goes to high-impedance

preventing “floating” inputs and eliminating the need for pullup/

down resistors.

OEAB 1

CLKENAB 56

CLKAB 55

2

LEAB

28

LEBA

CLKBA 30

CLKENBA 29

OEBA 27

A1 3

CE

1D

C1

CLK

CE

1D

C1

CLK

54 B1

To 17 Other Channels

1

PS8157A 11/06/00

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