GTLP18T612MEA 데이터 시트보기 (PDF) - Fairchild Semiconductor

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GTLP18T612MEA

18-Bit LVTTL/GTLP Universal Bus Transceiver

Fairchild Semiconductor 

Test Circuits and Timing Waveforms

Test Circuit for A Outputs

Test Circuit for B Outputs

Test

S

tPLH/tPHL Open

tPLZ/tPZL 6V

tPHZ/tPZH GND

Note A: CL includes probes and Jig capacitance.

Voltage Waveform - Propagation Delay Times

Note B: For B Port, CL = 30 pF is used for worst case.

Voltage Waveform - Setup and Hold Times

Voltage Waveform - Pulse Width

Voltage Waveform - Enable and Disable times

Output Waveform 1 is for an output with internal conditions such that the

output is LOW except when disabled by the control output.

Output Waveform 2 is for an output with internal conditions such that the

output is HIGH except when disabled by the control output.

Input and Measure Conditions

A or LVTTL B or GTLP

Pins

Pins

VinHIGH

3.0

1.5

VinLOW

0.0

0.0

VM

1.5

1.0

VX

VOL + 0.3V N/A

VY

VOH − 0.3V N/A

All input pulses have the following characteristics: Frequency = 10MHz, tRISE = tFALL = 2 ns (10% to 90%), ZO = 50Ω.

The outputs are measured one at a time with one transition per measurement.

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