LSM330DL 데이터 시트보기 (PDF) - STMicroelectronics
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LSM330DL Datasheet PDF : 54 Pages
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LSM330DL
Module specifications
2.4.2
I2C - inter-IC control interface
The values given in the following table are subject to the general operating conditions for
Vdd and TOP.
Table 7. I2C slave timing values
Symbol
Parameter(1)
I2C standard mode
Min
Max
I2C fast mode (1)
Min
Max
Unit
f(SCL)
SCL clock frequency
0
100
0
400
kHz
tw(SCLL) SCL clock low time
4.7
1.3
µs
tw(SCLH) SCL clock high time
4.0
0.6
tsu(SDA) SDA setup time
250
100
ns
th(SDA) SDA data hold time
0.01
3.45
0
0.9
µs
tr(SDA) tr(SCL) SDA and SCL rise time
tf(SDA) tf(SCL) SDA and SCL fall time
1000 20 + 0.1Cb (2)
300
ns
300 20 + 0.1Cb (2)
300
th(ST)
START condition hold time
4
0.6
tsu(SR) Repeated START condition setup time 4.7
0.6
tsu(SP)
STOP condition setup time
4
0.6
µs
tw(SP:SR)
Bus free time between STOP and
START condition
4.7
1.3
1. SCL (SCL_A/G pin), SDA (SDA_A/G pin)
Figure 4. I2C slave timing diagram (3)
SDA
START
REPEATED
START
tsu(SR)
tw(SP:SR)
START
tf(SDA)
SCL
tr(SDA)
tsu(SDA)
th(SDA)
tsu(SP)
STOP
th(ST) tw(SCLL)
tw(SCLH)
tr(SCL)
tf(SCL)
1. Data based on standard I2C protocol requirement, not tested in production.
2 Cb = total capacitance of one bus line, in pF
3. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
AM09238V1
Doc ID 022018 Rev 1
15/54
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