LH1560F 데이터 시트보기 (PDF) - Sharp Electronics
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LH1560F Datasheet PDF : 30 Pages
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SHARP
LHl560F
9
EIO,
EIOp
yI-ylso
*When set to VDD level ‘H”.segment mode is set.
Input/Output
pin for chip selection
*When L/R input is at VSS level “L”, EIO, is set for output, and EIO:
is set for input.
*When L/R input is at Voo level “H”, EIO, is set for input, and EIOz
is set for output.
*During output. set to “H” while LP*E is “H” and after 160-bits of
data have been read, set to “L” for one cycle (from falling edge to
falling edge of XCK). after which it returns to “H”.
*During input. after the LP signal is input, the chip is selected
while EI is set to “L”. After 160-bits of data have been read, the
chip is deselected.
LC driver output pins
*Corresponding directly to each bit of the data latch, one level
(Vo. VIZ? v43* or VSS> is selected and output.
Table of truth values is shown in 7-2-l.
V~~R.V,~~
v43R* V43L
rEIO,
I
EIOz
LP
L/R
*Normally. the bias voltage used is set by a resistor divider.
*Ensure that voltages are set such that VSS<V43<V,z<Vo.
*To further reduce the difference between the output waveforms of LC
driver output pins Y, and YIBo, externally connect ViR and V,L
(i=O. 12, 43).
Bidirectional
shift register shift data input/output
pin
*Output pin when L/R is at VSS level “L”. input pin when L/R is at
VDo level “H”.
*When EIO, is used as input pin, it will be pull-doen.
-When EIO, is used as output pin,it won’t be pull-down.
Bidirectional
shift register shift data input/output
pin
*Input pin when L/R is at VSS level “L”. output pin when L/R is at
VDD level “H”.
*When EIOz is used as input pin, it will be pull-down.
*When EIOp is used as output pin, it won’t be pull-down.
Bidirectional
shift register shift clock pulse input pin
*Data is shifted on the falling edge of the clock pulse.
Bidirectional
shift register shift direction selection pin
*Data is shifted from Ylso to Y, when set to VSS level “L”. and data
is shifted from Y, to Ytso when set to VDo level “H”.
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