K8P5616UZB 데이터 시트보기 (PDF) - Samsung
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K8P5616UZB Datasheet PDF : 60 Pages
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K8P5616UZB
Rev. 1.0
datasheet NOR FLASH MEMORY
10.9 Read While Write
The K8P5616UZB provides multi-bank memory architecture that divides the memory array into four banks. The device is capable of reading data from
one bank and writing data to the other bank simultaneously. This is so called the Read While Write operation with multi-bank architecture; this feature pro-
vides the capability of executing the read operation during Program/Erase or Erase-Suspend-Program operation. The Read While Write operation is pro-
hibited during the chip erase operation. It is also allowed during erase operation when either single block or multiple blocks from same bank are loaded to
be erased. It means that the Read While Write operation is prohibited when blocks from one Bank and another blocks from the other Bank are loaded all
together for the multi-block erase operation.
10.10 Write Protect (WP)
The WP/ACC pin has two useful functions. The one is that certain block is protected by the hardware method not to use VID. The other is that program
operation is accelerated to reduce the program time (Refer to Accelerated program Operation Paragraph).
When the WP/ACC pin is asserted at VIL, the device can not perform program and erase operation in the outermost 64 Kword block (BA255 or BA0) on
end of the flash array independently of whether that block was protected or unprotected. The write protected blocks can only be read. This is useful
method to preserve an important program data.
When the WP/ACC pin is asserted at VIH, the device reverts the outermost 64Kword block on an end to default protection state. Note that the WP/ACC
pin must not be at VHH, for operations other than accelerated programming, or device damage may result.
10.11 Software Reset
The reset command provides that the bank is reseted to read mode or erase-suspend-read mode. The addresses are in don't Care state. The reset com-
mand is vaild between the sequence cycles in an erase command sequence before erasing begins, or in a program command sequence before program-
ming begins. This resets the bank in which was operating to read mode. if the device is be erasing or programming, the reset command is invalid until the
operation is completed. Also, the reset command is valid between the sequence cycles in an autoselect command sequence. In the autoselect mode, the
reset command returns the bank to read mode. If a bank entered the autoselect mode in the Erase Suspend mode, the reset command returns the bank
to erase-suspend-read mode. If DQ5 is high on erase or program operation, the reset command return the bank to read mode or erase-suspend-read
mode if the bank was in the Erase Suspend state.
10.12 Hardware Reset
The K8P5616UZB offers a reset feature by driving the RESET pin to VIL. When the RESET pin is held low(VIL) for at least a period of tRP, the device
immediatley terminates any operation in progress, tristates all outputs, and ignores all read/write commands for duration of the RESET pulse. The device
also resets the internal state machine to asynchronous read mode. If a hardware reset occurs during a program operation, the data at that particular loca-
tion will be lost. Once the RESET pin is taken high, the device requires 200ns of wake-up time until outputs are valid for read access. Also, note that all
the data output pins are tri-stated for the duration of the RESET pulse. The RESET pin may be tied to the system reset pin. If a system reset occurs dur-
ing the Internal Program and Erase Routine, the device will be automatically reset to the read mode ; this will enable the systems microprocessor to read
the boot-up firmware from the Flash memory.
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