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IA63484

Advanced CRT Controller

InnovASIC, Inc 

IA63484

Advanced CRT Controller

Figure 5: Display Screen Specification

hsync_n

HWS*

HSW HDS*

HC*

HWW*

HDW*

Display Screen Period

(Upper)

(Base)

(Window)

(Lower)

(Base)

Data Sheet

Timing Processor:

The Timing Processor generates the CRT synchronization signals and signals used internally

by the ACRTC. The details for this block are contained in the module specification for the

Display Processor.

CRT Interface:

The CRT Interface manages the communication between the frame buffer, the light pen and the

CRT. The frame buffer interface manages the frame buffer bus and selects display drawing or

refreshes address outputs. The light pen interface uses a 20-bit address register and a strobe input pin

(lpstb).

Copyright © 2001

innovASIC

The End of Obsolescence™

ENG 21101041200

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