FM24C256-S 데이터 시트보기 (PDF) - Unspecified

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FM24C256-S

256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect

Unspecified 

FM24C256

By Master

Start

Address & Data

S

Slave Address 0 A X Address MSB

A

Address LSB

A

By FM24C256

Acknowledge

Data Byte

Stop

AP

Figure 5. Single Byte Write

Start

By Master

Address & Data

Stop

S

Slave Address 0 A X Address MSB

A

Address LSB

A

Data Byte

A

Data Byte

AP

By FM24C256

Acknowledge

Figure 6. Multiple Byte Write

Read Operation

There are two types of read operations. They are

current address read and selective address read. In a

current address read, the FM24C256 uses the internal

address latch to supply the address. In a selective

read, the user performs a procedure to set the address

to a specific value.

Current Address & Sequential Read

As mentioned above the FM24C256 uses an internal

latch to supply the address for a read operation. A

current address read uses the existing value in the

address latch as a starting place for the read

operation. The system reads from the address

immediately following that of the last operation.

To perform a current address read, the bus master

supplies a device address with the LSB set to 1. This

indicates that a read operation is requested. After

receiving the complete device address, the

FM24C256 will begin shifting out data from the

current address on the next clock. The current address

is the value held in the internal address latch.

Beginning with the current address, the bus master

can read any number of bytes. Thus, a sequential read

is simply a current address read with multiple byte

transfers. After each byte, the internal address

counter will be incremented.

Each time the bus master acknowledges a byte, this

indicates that the FM24C256 should read out the next

sequential byte.

There are four ways to properly terminate a read

operation. Failing to properly terminate the read will

most likely create a bus contention as the FM24C256

attempts to read out additional data onto the bus. The

four valid methods are as follows.

1. The bus master issues a no-acknowledge in the

9th clock cycle and a stop in the 10th clock cycle.

This is illustrated in the diagrams below. This is

preferred.

2. The bus master issues a no-acknowledge in the

9th clock cycle and a start in the 10th.

3. The bus master issues a stop in the 9th clock

cycle.

4. The bus master issues a start in the 9th clock

cycle.

If the internal address reaches 7FFFh, it will wrap

around to 0000h on the next read cycle. Figures 7 and

8 show the proper operation for current address reads.

Selective (Random) Read

There is a simple technique that allows a user to

select a random address location as the starting point

for a read operation. This involves using the first

three bytes of a write operation to set the internal

address followed by subsequent read operations.

To perform a selective read, the bus master sends out

the device address with the lsb set to 0. This specifies

a write operation. According to the write protocol,

the bus master then sends the address bytes that are

loaded into the internal address latch. After the

FM24C256 acknowledges the address, the bus master

issues a Start condition. This simultaneously aborts

the write operation and allows the read command to

be issued with the device address LSB set to a 1. The

operation is now a current address read.

Rev 3.1

May 2005

Page 6 of 12

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