EBE21FD4AGFN 데이터 시트보기 (PDF) - Elpida Memory, Inc
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EBE21FD4AGFN Datasheet PDF : 22 Pages
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EBE21FD4AGFD, EBE21FD4AGFN
AMB Component Timing
For purposes of IDD testing, the following parameters are to be utilized.
Parameter
EI Assertion pass-thru timing
EI deassertion pass-thru timing
Symbol
tEI
propagate
tEID
min.
typ.
—
—
—
—
EI assertion duration
Resample pass-thru time
tEI
100
—
—
TBD
Resynch pass-thru Time
—
TBD
Bit lock Interval
tBitLock
—
—
Frame lock Interval
tFrameLock
—
—
Note: 1. The EI stands for ″Electrical Idle″.
max.
4
bit lock
—
—
—
119
154
Units
clks
clks
clks
ns
ns
frames
frames
Note
Power Specification Parameter and Test Conditions
Frequency (Mbps)
Parameter
Symbol
-6E
-5C
667
533
Power
Supply max. max. Unit
Idle Current,
single or last
DIMM
Idd_Idle_0
@1.5V 2.60 2.20 A
@1.8V 2.81 2.59 A
Total
8.58 7.53 W
Conditions
L0 state, idle (0 BW)
Primary channel enabled,
Secondary channel disabled
CKE high. Command and address lines
stable.
DRAM clock active.
Note
Idle Current, first
DIMM
Idd_Idle_1
@1.5V 3.40 3.00 A
@1.8V 2.80 2.57 A
Total
9.81 8.75 W
L0 state, idle (0 BW)
Primary and secondary channels enabled
CKE high. Command and address lines
stable.
DRAM clock active.
@1.5V 3.90 3.40 A
Active Power
Idd_Active_1 @1.8V 5.41 5.36 A
Total
15.56 14.69 W
@1.5V 3.70 3.20 A
Active Power,
data pass through
Idd_Active_2
@1.8V
2.32
2.14
A
Total
9.39 8.25 W
Training
@1.5V 4.00 3.50 A
Idd_Training
(for AMB spec. @1.8V 2.63 2.40 A
Not in SPD)
Total
10.44 9.22 W
L0 state
50% DRAM BW, 67% read, 33% write.
Primary and secondary channels enabled.
DRAM clock active, CKE high.
L0 state
50% DRAM BW to downstream DIMM,
67% read, 33% write.
Primary and secondary channels enabled.
CKE high. Command and address lines
stable.
DRAM clock active.
Primary and secondary channels enabled.
100% toggle on all channel lanes
DRAMs idle. 0 BW.
CKE high, Command and address lines
stable.
DRAM clock active.
Preliminary Data Sheet E0868E30 (Ver. 3.0)
11
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