CY7C1486BV25(2011) 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1486BV25
(Rev.:2011)
(Rev.:2011)
Cypress Semiconductor
CY7C1486BV25 Datasheet PDF : 34 Pages
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Truth Table
The truth table for CY7C1480BV25, CY7C1482BV25, and CY7C1486BV25 follows.[3, 4, 5, 6, 7]
Operation
Deselect cycle, power down
Deselect cycle, power down
Deselect cycle, power down
Deselect cycle, power down
Deselect cycle, power down
Sleep mode, power down
Read cycle, begin burst
Read cycle, begin burst
Write cycle, begin burst
Read cycle, begin burst
Read cycle, begin burst
Read cycle, continue burst
Read cycle, continue burst
Read cycle, continue burst
Read cycle, continue burst
Write cycle, continue burst
Write cycle, continue burst
Read cycle, suspend burst
Read cycle, suspend burst
Read cycle, suspend burst
Read cycle, suspend burst
Write cycle, suspend burst
Write cycle, suspend burst
Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ
None
H X XL
X
L
X
X
X L-H Tristate
None
L
L
XL
L
X
X
X
X L-H Tristate
None
L
X HL
L
X
X
X
X L-H Tristate
None
L
L
XL
H
L
X
X
X L-H Tristate
None
L
X HL
H
L
X
X
X L-H Tristate
None
X X XH X
X
X
X
X X Tristate
External
L
H
LL
L
X
X
X
L L-H
Q
External
L
H
LL
L
X
X
X
H L-H Tristate
External
L
H
LL
H
L
X
L
X L-H
D
External
L
H
LL
H
L
X
H
L L-H
Q
External
L
H
LL
H
L
X
H
H L-H Tristate
Next
X
X XL
H
H
L
H
L L-H
Q
Next
X
X
XL
H
H
L
H
H L-H Tristate
Next
H
X XL
X
H
L
H
L L-H
Q
Next
H X XL
X
H
L
H
H L-H Tristate
Next
X
X
XL
H
H
L
L
X L-H
D
Next
H X XL
X
H
L
L
X L-H
D
Current
X X XL
H
H
H
H
L L-H
Q
Current
X
X
XL
H
H
H
H
H L-H Tristate
Current
H X XL
X
H
H
H
L L-H
Q
Current
H X XL
X
H
H
H
H L-H Tristate
Current
X X XL
H
H
H
L
X L-H
D
Current
H X XL
X
H
H
L
X L-H
D
Notes
3. X = Do Not Care, H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6.
The SRAM always initiates
ADSP or with the assertion
a read cycle when ADSP is asserted, regardless of the
of ADSC. As a result, OE must be driven HIGH before
sthtaetestoafrtGoWf t,hBeWwErit,eocr yBcWleXt.oWernitaebslemtahye
occur only
outputs to
on subsequent clocks after the
tristate. OE is a do not care for
the remainder of the write cycle
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive
or when the device is deselected, and all data bits behave as outputs when OE is active (LOW).
Document Number: 001-15143 Rev. *H
Page 11 of 34
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