AD5424YCPZ(2016) 데이터 시트보기 (PDF) - Analog Devices
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AD5424YCPZ
(Rev.:2016)
(Rev.:2016)
Analog Devices
AD5424YCPZ Datasheet PDF : 28 Pages
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Data Sheet
AD5424/AD5433/AD5445
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless
otherwise noted. DC performance measured with OP177 and ac performance measured with AD8038, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
AD5424
Resolution
Relative Accuracy
Differential Nonlinearity
AD5433
Resolution
Relative Accuracy
Differential Nonlinearity
AD5445
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error Temperature Coefficient1
Output Leakage Current1
REFERENCE INPUT1
Reference Input Range
VREF Input Resistance
RFB Resistance
Input Capacitance
Code Zero Scale
Code Full Scale
DIGITAL INPUTS/OUTPUT1
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH
Output Low Voltage, VOL
Input Leakage Current, IIL
Input Capacitance
DYNAMIC PERFORMANCE1
Reference Multiplying Bandwidth
Output Voltage Settling Time
Min
Typ Max
8
±0.25
±0.5
10
±0.5
±1
12
±1
–1/+2
±10
±5
±10
±20
±10
8
10 12
8
10 12
36
58
1.7
0.6
VDD − 1
VDD − 0.5
0.4
0.4
1
4 10
10
Measured to ±16 mV of full scale
Measured to ±4 mV of full scale
Measured to ±1 mV of full scale
Digital Delay
10% to 90% Settling Time
Digital-to-Analog Glitch Impulse
Multiplying Feedthrough Error
30 60
35 70
80 120
20 40
15 30
2
70
48
Unit
Bits
LSB
LSB
Bits
LSB
LSB
Bits
LSB
LSB
mV
ppm FSR/°C
nA
nA
V
kΩ
kΩ
pF
pF
V
V
V
V
V
V
µA
pF
MHz
ns
ns
ns
ns
ns
nV-s
dB
dB
Test Conditions/Comments
Guaranteed monotonic
Guaranteed monotonic
Guaranteed monotonic
Data = 0×0000, TA = 25°C, IOUT1
Data = 0×0000, T = −40°C to +125°C, IOUT1
Input resistance TC = –50 ppm/°C
Input resistance TC = –50 ppm/°C
VDD = 4.5 V to 5 V, ISOURCE = 200 µA
VDD = 2.5 V to 3.6 V, ISOURCE = 200 µA
VDD = 4.5 V to 5 V, ISINK = 200 µA
VDD = 2.5 V to 3.6 V, ISINK = 200 µA
VREF = ±3.5 V; DAC loaded all 1s
VREF = ±3.5 V, RLOAD = 100 Ω, DAC latch
alternately loaded with 0s and 1s
Interface delay time
Rise and fall time, VREF = 10 V, RLOAD = 100 Ω
1 LSB change around major carry, VREF = 0 V
DAC latch loaded with all 0s, VREF = ±3.5 V
Reference = 1 MHz
Reference = 10 MHz
Rev. E | Page 3 of 28
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