25AA1024-I 데이터 시트보기 (PDF) - Microchip Technology

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25AA1024-I

1 Mbit SPI Bus Serial EEPROM

Microchip Technology 

25AA1024/25LC1024

2.2 Write Sequence

Prior to any attempt to write data to the 25XX1024, the

write enable latch must be set by issuing the WREN

instruction (Figure 2-4). This is done by setting CS low

and then clocking out the proper instruction into the

25XX1024. After all eight bits of the instruction are

transmitted, the CS must be brought high to set the

write enable latch. If the write operation is initiated

immediately after the WREN instruction without CS

being brought high, the data will not be written to the

array because the write enable latch will not have been

properly set.

A write sequence includes an automatic, self timed

erase cycle. It is not required to erase any portion of the

memory prior to issuing a Write command.

Once the write enable latch is set, the user may

proceed by setting the CS low, issuing a WRITE instruc-

tion, followed by the 24-bit address, with seven MSBs

of the address being “don’t care” bits, and then the data

to be written. Up to 256 bytes of data can be sent to the

device before a write cycle is necessary. The only

restriction is that all of the bytes must reside in the

same page. When doing a write of less than 256 bytes

FIGURE 2-2:

BYTE WRITE SEQUENCE

the data in the rest of the page is refreshed along with

the data bytes being written. For this reason,

endurance is specified per page.

Note:

Page write operations are limited to writing

bytes within a single physical page,

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples of the page buffer size (or

‘page size’), and end at addresses that are

integer multiples of page size – 1. If a

Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being written to the next page as might be

expected. It is therefore necessary for the

application software to prevent page write

operations that would attempt to cross a

page boundary.

For the data to be actually written to the array, the CS

must be brought high after the Least Significant bit (D0)

of the nth data byte has been clocked in. If CS is

brought high at any other time, the write operation will

not be completed. Refer to Figure 2-2 and Figure 2-3

for more detailed illustrations on the byte write

sequence and the page write sequence, respectively.

While the write is in progress, the STATUS register may

be read to check the status of the WPEN, WIP, WEL,

BP1 and BP0 bits (Figure 2-6). A read attempt of a

memory array location will not be possible during a

write cycle. When the write cycle is completed, the

write enable latch is reset.

CS

SCK

SI

SO

0 1 2 3 4 5 6 7 8 9 10 11

Twc

29 30 31 32 33 34 35 36 37 38 39

Instruction

24-bit Address

Data Byte

0 0 0 0 0 0 1 0 23 22 21 20

2 1 07 6 5 4 3 2 1 0

High-Impedance

DS21836D-page 8

Preliminary

© 2007 Microchip Technology Inc.

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