WM8706SEDS 데이터 시트보기 (PDF) - Wolfson Microelectronics plc
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WM8706SEDS Datasheet PDF : 26 Pages
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WM8706
MASTER CLOCK TIMING
XTI
tXTIL
tXTIH
tXTIY
Production Data
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, XTI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
Master Clock Timing Information
XTI Master clock pulse width high
tXTIH
XTI Master clock pulse width low
tXTIL
XTI Master clock cycle time
tXTIY
XTI Duty cycle
TEST CONDITIONS
MIN
TYP
13
13
26
40:60
MAX
60:40
UNIT
ns
ns
ns
DIGITAL AUDIO INTERFACE
tBCH
tBCL
BCKIN
tBCY
LRCIN
DIN
tDS
tLRH
tLRSU
tDH
Figure 2 Digital Audio Data Timing
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, XTI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
BCKIN cycle time
tBCY
BCKIN pulse width high
BCKIN pulse width low
LRCIN set-up time to
BCKIN rising edge
tBCH
tBCL
tLRSU
LRCIN hold time from
tLRH
BCKIN rising edge
DIN set-up time to BCKIN
tDS
rising edge
DIN hold time from BCKIN
tDH
rising edge
TEST CONDITIONS
MIN
TYP
40
16
16
8
8
8
8
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
w
PD Rev 4.1 July 2005
8
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