V827332U04S 데이터 시트보기 (PDF) - Mosel Vitelic, Corp
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V827332U04S Datasheet PDF : 14 Pages
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MOSEL VITELIC
V827332U04S
Serial Presence Detect Information (cont.)
Byte #
Function described
29 Minimum RAS to CAS delay(=tRCD)
30 Minimum active to precharge time(=tRAS)
31 Module ROW density
32 Command and address signal input setup time
33 Command and address signal input hold time
34 Data signal input setup time
35 Data signal input hold time
36-40 Superset information (may be used in future)
41
42
43
44
45
46-61
SDRAM device minimum active to active/auto-refresh time
(=tRC)
SDRAM device minimum active to autorefresh to active/auto-refresh
time (=tRFC)
SDRAM device maximum device cycle time (=tCK MAX)
SDRAM device maximum skew between DQS and DQ signals
(=tDQSQ)
SDRAM device maximum read datahold skew factor (=tQHS)
Superset information (may be used in future)
62 SPD data revision code
63 Checksum for Bytes 0 ~ 62
64 Manufacturer JEDEC ID code
65 -71 ....... Manufacturer JEDEC ID code
72 Manufacturing location
73-90 Module part number (ASCII)
91 Manufacturer revison code (For PCB)
92 Manufacturer revison code (For component)
93 Manufacturing date (Week)
94 Manufacturing date (Year)
95~98 Assembly serial #
99~127 Manufacturer specific data (may be used in future)
128~255 Open for customer use
Function Supported
A1 B0 B1
20ns 20ns 18ns
50ns 45ns 45ns
128MB
1.1ns 0.9ns 0.9ns
1.1ns 0.9ns 0.9ns
0.6ns 0.5ns 0.5ns
0.6ns 0.5ns 0.5ns
-
70ns 65ns 60ns
Hex value
A1 B0 B1
50h 50h 48h
32h 2Dh 2Dh
20h
B0h 90h 90h
B0h 90h 90h
60h 50h 50h
60h 50h 50h
00h
46h 41h 3Ch
80ns 75ns 67ns 50h 4Bh 43h
12ns 12ns 12ns 30h 30h 30h
0.6ns 0.5ns 0.5ns 3Ch 32h 32h
1ns 0.75ns 0.75ns A0h 75h 75h
-
00h
Initial release
00h
-
DDh 23h C2h
Mosel Vitelic
40h
Mosel Vitelic
00h
01h
V827332U04S
0
00
0
00
-
-
-
-
-
-
Undefined
00h
Undefined
00h
V827332U04S Rev. 1.2 March 2002
6
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