NJU6682CH 데이터 시트보기 (PDF) - Japan Radio Corporation

부품명

상세내역

일치하는 목록

NJU6682CH

160-common x 132-segment DOT MATRIX LCD DRIVER FOR 4 GRAY SCALE

Japan Radio Corporation  

NJU6682

1-9)The LCD drive circuit system

1-9-1)The LCD drive circuit

The common output has a shift register and it forwards a common scan signal in order. It outputs liquid crystal

drive voltage in the combination of the display data, the common scan signal, the inner FR signal, the liquid crystal

flowing mutually signal. A segment, common output corrugated example are shown in figure 2.

1-9-2)Display Data Latch-Circuit

The display data latch circuit is the latch which stores the display data of 132 x 2 bits which are addressed by the

Z-address counter and are output from the display data RAM to the LCD drive circuit every 1 common 1 period

temporarily. Data in the display data RAM is changed and not held because display turn to Positive / Negative ( In

case of Black & White display ),displaying on / off, Static Drive On / Off instructions are controls data in this latch

circuit.

1-9-3)Gray Scale / Black & White Control Circuit

A Gray Scale control circuit chooses the gray scale level which was set by the command instruction from the gray

scale data of 264 bits which latched with the display data latch circuit and is output for LCD drive output Sn. A Black

& White display control circuit chooses layer which was set by the command instruction from the 264 bit Black &

White data which latched with the display data latch circuit and is output for LCD drive output Sn.

1-9-4)Z-Counter, Signal Genelate of Display Data Latch Circuit

It generates a latch signal to the clock(CL) to Z-counter and to the display data latch circuit. It synchronizes with

the internal display clock and the line address of the display data RAM occurs, and the display data of 132 x 2 bits

synchronizes with the display clock, latches by the display data latch circuit and is output by the gray scale control /

Black & White display control circuit. The read out to the display data LCD drive circuit is independent totally with the

access to the display data RAM from the CPU.

1-9-5)Display Timing Genelate Circuit

The display timing occurrence circuit generates the internal timing of the display system by the master clock and

the internal FR signal. As for it, the internal FR signal and the LCD flowing mutually signal make the drive corrugation

of the 2 frame alternating current drive or the n-line inverting drive method occur to the LCD Driving circuit.

1-9-6)FRC / PWM Control Circuit

PWM & FRC(Frame Rate Control) to realize 4Gray Scale display function.

Share Link: