U631H16 데이터 시트보기 (PDF) - Unspecified
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U631H16 Datasheet PDF : 12 Pages
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U631H16
Symbol
No. Software Controlled STORE/RECALL
Cyclel, n
Alt.
IEC
25
35
45
Unit
Min. Max. Min. Max. Min. Max.
25 STORE/RECALL Initiation Time
26 Chip Enable to Output Inactiveo
27 STORE Cycle Timep
28 RECALL Cycle Timeq
29 Address Setup to Chip Enabler
30 Chip Enable Pulse Widthr, s
31 Chip Disable to Address Changer
tAVAV
tcR
25
35
45
ns
tELQZ tdis(E)SR
600
600
600 ns
tELQXS td(E)S
10
10
10 ms
tELQXR td(E)R
20
20
20 µs
tAVELN tsu(A)SR 0
0
0
ns
tELEHN tw(E)SR 20
25
35
ns
tEHAXN th(A)SR
0
0
0
ns
n: The software sequence is clocked with E controlled READs.
o: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
p: Note that STORE cycles (but not RECALL) are aborted by VCC < VSWITCH (STORE inhibit).
q: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
VSWITCH once it has been exceeded for the RECALL to function properly.
r: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
s: If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
SOFTWARE CONTROLLED STORE/RECALL CYCLEr, s, t, u (E = HIGH after STORE initiation)
25
25
Ai
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tcR
ADDRESS 1
tcR
ADDRESS 6
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
31
30
E
29
tw(E)SR
31
tsu(A)SR
th(A)SR
29
tsu(A)SR
30
tw(E)SR
th(A)SR
5
tdis(E)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
27 / 28
DQi
High Impedance VALID
Output
VALID
26
td(E)S / td(E)R AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tdis(E)SR
SOFTWARE CONTROLLED STORE/RECALL CYCLEr, s, t, u (E = LOW after STORE initiation)
Ai AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
25
tcR
ADDRESS 1
30
E
29
tw(E)SR
31
tsu(A)SR
th(A )SR
DQi
Output
High Impedance
VALID
29
tsu(A )SR
ADDRESS 6
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
31
th(A)SR
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
27 / 28
td(E)S / td(E)R
VALID
26
tdis(E)SR
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
t: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U631H16 performs a STORE
or RECALL.
u: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
8
December 12, 1997
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