AD760(RevA) 데이터 시트보기 (PDF) - Analog Devices
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AD760 Datasheet PDF : 12 Pages
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AD760
AD760
REFI N
25
R1
50Ω
9.95kΩ
+10V REF
10kΩ
10kΩ
REFOUT
26
24
SPAN/
BIP OFF
MAIN DAC
23 VOUT
Figure 6a. 0 V to ±10 V Bipolar Voltage Output
Gain Error can be adjusted to zero using the circuit shown in
Figure 6b. Note that gain adjustment changes the Bipolar Zero
by one half of the variation made to the full-scale output value.
Therefore, to eliminate iterating between Zero (calibration) and
Gain adjustment the following procedure is recommended.
STEP 1 . . . ZERO ADJUST
Initiate Calibration Sequence.
STEP 2 . . . GAIN ADJUST
Insure the CALOK pin remains high throughout the gain ad-
justment process. Turn all bits on and measure the output error
relative to the full-scale output of 9.99695 V. Adjust R1 until
the output is minus two times the full-scale output error. For
example, if the output error is –1 mV, adjust the output 2 mV
higher than the previous full-scale error.
STEP 3 . . . ZERO ADJUST
Initiate Calibration Sequence. The AD760 will calibrate Bipolar
Zero and the resulting Gain Error will be very small. Reload the
DAC with all ones to check the full-scale output error.
AD760
REFI N
25
9.95kΩ
+10V REF
10kΩ
10kΩ
MAIN DAC
REFOUT
26
24
SPAN/
BIP OFF
23 VOUT
R1
100Ω
Figure 6b. 0 V to ±10 V Bipolar Voltage Output Gain
Adjustment
It should be noted that using external resistors will introduce a
small temperature drift component beyond that inherent in the
AD760. The internal resistors are trimmed to ratio-match and
temperature-track other resistors on chip, even though their
absolute tolerances are ±20% and absolute temperature coeffi-
cients are approximately –50 ppm/°C. In the case that external
resistors are used, the temperature coefficient mismatch be-
tween internal and external resistors, multiplied by the sensitiv-
ity of the circuit to variations in the external resistor value, will
be the resultant additional temperature drift.
INTERNAL/EXTERNAL REFERENCE USE
The AD760 has an internal low noise buried Zener diode refer-
ence that is trimmed for absolute accuracy and temperature co-
efficient. This reference is buffered and optimized for use in a
high speed DAC and will give long-term stability equal or supe-
rior to the best discrete Zener diode references. The perfor-
mance of the AD760 is specified with the internal reference
driving the DAC and with the DAC alone (for use with a preci-
sion external reference).
The internal reference has sufficient buffering to drive external
circuitry in addition to the reference currents required for the
DAC (typically 1 mA to REF IN and 1 mA to BIPOLAR OFF-
SET). A minimum of 2 mA is available for driving external
loads. The AD760 reference output should be buffered with an
external op amp if it is required to supply more than 4 mA total
current. The reference is tested and guaranteed to ±0.1% max
error.
It is also possible to use external references other than 10 volts
with slightly degraded linearity specifications. The recom-
mended range of reference voltages is +5 V to +10.24 V. For
example, by using the AD586 5 V reference, outputs of 0 V to
+5 V or ±5 V can be realized. Using the AD586 voltage refer-
ence makes it possible to operate the AD760 with ±12 V sup-
plies with 10% tolerances.
Figure 7 shows the AD760 using the AD586 precision 5 V refer-
ence in the bipolar configuration. The highest grade AD586MN
is specified with a drift of 2 ppm/°C. This circuit includes an
optional potentiometer that can be used to adjust the gain error
in a manner similar to that described in the Bipolar Configura-
tion section. Use +4.999847 V as the full-scale output value.
The AD760 can also be used with the AD587, 10 V reference,
using the same configuration shown in Figure 7 to produce a
±10 V output. The highest grade AD587L is specified at
5 ppm/°C.
AD760
9.95kΩ
+10V REF
10kΩ
10kΩ
MAIN DAC
REFI N
25
100Ω
+VCC
2
26 REFOUT
24
SPAN/BIP OFF
AD586
6
VOUT
4
23 VOUT
Figure 7. Using the AD760 with the AD586 5 V Reference
OUTPUT SETTLING AND GLITCH
The AD760’s output buffer amplifier typically settles to within
0.0008% FS (1/2 LSB) of its final value in 8 µs for a full-scale
step. Figures 8a and 8b show settling for a full scale and an
LSB step, respectively, with a 2 k , 1000 pF load applied. The
guaranteed maximum settling time at +25°C for a full-scale step
is 13 µs with this load. The typical settling time for a 1 LSB step
is 2.5 µs.
–8–
REV. A
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