TB62706BFG 데이터 시트보기 (PDF) - Marktech Optoelectronics

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TB62706BFG

Bi-CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC

Marktech Optoelectronics 

BLOCK DIAGRAM

TIMING DIAGRAM

TB62706BNG/BFG

Note: Latches are level sensitive, not rising edges sensitive and not syncronus CLOCK.

Input of LATCH- terminal to H Level, data passes latches, and input to L level, data hold latches.

Input of ENABLE- terminal to H level, all output (OUT0~15) do off.

2

2004-06-24

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