tm TE
CH
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
tR C
Ad d re s s
DO U T
tOH
tA A
READ CYCLE 2
(Chip Select Controlled)
CS
DOUT
tC L Z
tA C S
READ CYCLE 3
(Output Enable Controlled)
A d dr es s
OE
CS
DOUT
tR C
tA A
tAOE
tOLZ
tA CS
tC LZ
Taiwan Memory Technology, Inc. reserves the right P. 7
to change products or specifications without notice.
T15V256A
tO H
tC H Z
tO H
t OH Z
tCHZ
DON'T CARE
UNDEFINED
Publication Date: SEP. 2001
Revision:A