ADG406 데이터 시트보기 (PDF) - Analog Devices
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ADG406 Datasheet PDF : 20 Pages
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ADG426 TIMING DIAGRAMS
3V
WR
50%
50%
0V
tW
3V
A0, A1, A2, (A3)
EN
0V
tS
2V
tH
0.8V
Figure 4. Timing Sequence for Latching the Switch Address and Enable Inputs
Figure 4 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive;
therefore, while WR is held low, the latches are transparent and
the switches respond to the address and enable inputs. This
input data is latched on the rising edge of WR.
ADG406/ADG407/ADG426
3V
RS
0V
50%
50%
tW
tOFF (RS)
V0
SWITCH
OUTPUT
0V
0.8V0
Figure 5. Reset Pulse Width and Reset Turn Off Time
Figure 5 shows the reset pulse width, trs, and the reset turn off
time, tOFF (RS).
Note that all digital input signals rise and fall times are
measured from 10% to 90% of 3 V; tR = tF = 20 ns.
Rev. B | Page 7 of 20
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