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LTC1606AC 데이터 시트보기 (PDF) - Linear Technology

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LTC1606AC
Linear
Linear Technology Linear
LTC1606AC Datasheet PDF : 16 Pages
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LTC1606
TEST CIRCUITS
Load Circuit for Access Timing
5V
DBN
1k
DBN
30pF
1k
30pF
A. Hi-Z TO VOH AND VOL TO VOH
1606 TC01
B. Hi-Z TO VOL AND VOH TO VOL
Load Circuit for Output Float Delay
5V
DBN
1k
30pF
A. VOH TO Hi-Z
1k
DBN
30pF
1606 TC02
B. VOL TO Hi-Z
APPLICATIO S I FOR ATIO
Conversion Details
The LTC1606 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 16-bit or two byte parallel output. The
ADC is complete with a precision reference and an internal
clock. The control logic provides easy interface to micro-
processors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and R/C inputs. At
the start of conversion, the successive approximation
register (SAR) is reset. Once a conversion cycle has
begun, it cannot be restarted.
During the conversion, the internal 16-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, VIN is connected through the resistor divider to
RIN1
VIN
RIN2
SAMPLE CSAMPLE
HOLD
CDAC
DAC
VDAC
SAMPLE
SI
+
COMPARATOR
S
A
R
16-BIT
LATCH
1606 • F01
Figure 1. LTC1606 Simplified Equivalent Circuit
8
the sample-and-hold capacitor during the acquire phase
and the comparator offset is nulled by the autozero switches.
In this acquire phase, a minimum delay of 1.5µs will
provide enough time for the sample-and-hold capacitor to
acquire the analog signal. During the convert phase, the
autozero switches open, putting the comparator into the
compare mode. The input switch switches CSAMPLE to
ground, injecting the analog input charge onto the sum-
ming junction. This input charge is successively com-
pared with the binary-weighted charges supplied by the
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the DAC output
balances the VIN input charge. The SAR contents (a 16-bit
data word) that represents the VIN are loaded into the
16-bit output latches.
Driving the Analog Inputs
The nominal input range for the LTC1606 is ±10V or
(±4 • VREF) and the input is overvoltage protected to ±25V.
The input impedance is typically 10k, therefore, it should
be driven with a low impedance source. Wideband noise
coupling into the input can be minimized by placing a
1000pF capacitor at the input as shown in Figure 2. An
NPO-type capacitor gives the lowest distortion. Place the
200
AIN
1000pF
33.2k
VIN
LTC1606
CAP
1606 • F02
Figure 2. Analog Input Filtering
1606fa

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