R8A77301 데이터 시트보기 (PDF) - Renesas Electronics

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R8A77301

32-Bit RISC Microcomputer

Renesas Electronics 

ETU

FIFO

H-UDI

INTC

JTAG

LSB

MMU

MSB

PFC

RISC

SCIF

TLB

TMU

UART

UBC

WDT

Elementary Time Unit

First-In First-Out

User Debug Interface

Interrupt Controller

Joint Test Action Group

Least Significant Bit

Memory Management Unit

Most Significant Bit

Pin Function Controller

Reduced Instruction Set Computer

Serial Communication Interface with FIFO

Translation Lookaside Buffer

Timer Unit

Universal Asynchronous Receiver/Transmitter

User Break Controller

Watch Dog Timer

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Rev. 1.00 Sep. 19, 2007 Page viii of xlviii

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