PI6C103H 데이터 시트보기 (PDF) - Pericom Semiconductor Corporation
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PI6C103H Datasheet PDF : 12 Pages
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PI6C103
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AC Timing
Figure 1. Host Clock
to PCI CLK Offset
Parameters
tHKP (2.5V)
tHKH (2.5V)
tHKL (2.5V)
tHRISE (2.5V)
tHFALL (2.5V)
tJITTER (2.5V)
Duty Cycle (2.5V)
tHSKW (2.5V)
tPZL, tPZH
tPLZ, tPHZ
tHSTB
tPKP
tPKPS
tPKH
tPKL
tPSKW
tHPOFFSET
tPSTB
Host CLK period
Host CLK high time
Host CLK low time
Host CLK rise time
Host CLK fall time
Host CLK Jitter
Measured at 1.25V
Host Bus CLK Skew
Output enable delay
Output disable delay
Host CLK Stabilization from power-up
PCI CLK period
PCI CLK period stability
PCI CLK high time
PCI CLK low time
PCI Bus CLK Skew
Host to PCI Clock Offset
PCI CLK Stabilization from power-up
66 MHz
Min. Max.
15.0
15.5
5.2
5.0
0.4
1.6
0.4
1.6
250
45
55
175
1.0
8.0
1.0
8.0
3
30.0
∝
500
12.0
12.0
500
1.5
4.0
3
100 MHz
Min. Max.
10.0 10.5
3.0
2.8
0.4
1.6
0.4
1.6
250
45
55
175
1.0
8.0
1.0
8.0
3
30.0
∝
500
12.0
12.0
500
1.5
4.0
3
Units
ns
ps
%
ps
ns
ms
ns
ps
ns
ps
ns
ms
230
PS8315-2 04/08/99
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