MD56V62160 데이터 시트보기 (PDF) - Oki Electric Industry

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MD56V62160

4-Bank x 1,048,576-Word x 16-Bit SYNCHRONOUS DYNAMIC RAM

Oki Electric Industry 

¡ Semiconductor

MD56V62160/H

PIN DESCRIPTION

CLK

Fetches all inputs at the "H" edge.

CS

Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,

UDQM and LDQM.

CKE

Masks system clock to deactivate the subsequent CLK operation.

If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is

deactivated. CKE should be asserted at least one cycle prior to a new command.

Address

Row & column multiplexed.

Row address: RA0 – RA11

Column address: CA0 – CA7

A12, A13

(BA1, BA0)

RAS

CAS

WE

Bank Access pins. These pins are dedicated to select one of 4 banks.

Functionality depends on the combination. For details, see the function truth table.

UDQM,

LDQM

Masks the read data of two clocks later when UDQM and LDQM are set "H" at the "H" edge of the clock signal.

Masks the write data of the same clock when UDQM and LDQM are set "H" at the "H" edge of the clock signal.

UDQM controls upper byte and LDQM controls lower byte.

DQi

Data inputs/outputs are multiplexed on the same pin.

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