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MC74LVX259D

8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter

ON Semiconductor 

MC74LVX259

TIMING REQUIREMENTS Input tr = tf = 3.0 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tw

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tsu

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ th

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tr, tf

Parameter

Minimum Pulse Width,

Reset or Enable

(Figure 8)

Minimum Setup Time,

Address or Data to Enable

(Figure 8)

Minimum Hold Time,

Enable to Address or Data

(Figure 7 or 8)

Maximum Input,

Rise and Fall Times

(Figure 5)

Test Conditions

VCC = 2.7 V

VCC = 3.3 V ± 0.3 V

VCC = 2.7 V

VCC = 3.3 V ± 0.3 V

VCC = 2.7 V

VCC = 3.3 V ± 0.3 V

VCC = 2.7 V

VCC = 3.3 V ± 0.3 V

TA = 25°C

TA = ≤ 85°C

Min Typ Max Min Max Unit

4.5

5.0

ns

4.5

5.0

4.0

4.0

ns

3.0

3.0

2.0

2.0

ns

2.0

2.0

400

300

ns

300

300

VCC

tr

DATA

IN

tPLH

50%

OUTPUT

Q

50%

DATA

tf

IN

VCC

ADDRESS

SELECT

50%

tPHL

GND

50%

tPHL

OUTPUT

Q

50%

tPHL

GND

VCC

GND

VCC

GND

Figure 5. Switching Waveform

Figure 6. Switching Waveform

DATA IN

ENABLE

OUTPUT Q

tw

50%

tPHL

tw

50%

50%

tPHL

VCC

GND

DATA IN

VCC

RESET

GN

D

OUTPUT Q

tw

50%

tPHL

50%

VCC

GND

VCC

GND

Figure 7. Switching Waveform

Figure 8. Switching Waveform

DATA IN OR

ADDRESS

SELECT

ENABLE

50%

tsu

th(H)

50%

Figure 9. Switching Waveform

TEST POINT

VCC

th(H)

GND

tsu

VCC

OUTPUT

DEVICE

UNDER

TEST

CL*

GND

*Includes all probe and jig capacitance

Figure 10. Test Circuit

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