MC54HCT138A 데이터 시트보기 (PDF) - Motorola => Freescale

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MC54HCT138A

1-of-8 Decoder/ Demultiplexer

Motorola => Freescale 

MC54/74HC138A

INPUT A

tPLH

OUTPUT Y

SWITCHING WAVEFORMS

VALID

50%

50%

VALID

tPHL

Figure 1.

tr

VCC

INPUT CS1

90%

50%

GND

10%

tPHL

90%

50%

OUTPUT Y

10%

tTHL

Figure 2.

tf

VCC

GND

tPLH

tTLH

INPUT

90%

50%

CS2, CS3 10%

OUTPUT Y

tf

tPHL

90%

50%

10%

tTHL

Figure 3.

tr

VCC

GND

tPLH

tTLH

DEVICE

UNDER

TEST

TEST POINT

OUTPUT

CL*

* Includes all probe and jig capacitance

Figure 4. Test Circuit

PIN DESCRIPTIONS

ADDRESS INPUTS

A0, A1, A2 (Pins 1, 2, 3)

Address inputs. These inputs, when the chip is selected,

determine which of the eight outputs is active–low.

CONTROL INPUTS

CS1, CS2, CS3 (Pins 6, 4, 5)

Chip select inputs. For CS1 at a high level and CS2, CS3

at a low level, the chip is selected and the outputs follow the

Address inputs. For any other combination of CS1, CS2, and

CS3, the outputs are at a logic high.

OUTPUTS

Y0 – Y7 (Pins 15, 14, 13, 12, 11, 10, 9, 7)

Active–low Decoded outputs. These outputs assume a low

level when addressed and the chip is selected. These out-

puts remain high when not addressed or the chip is not

selected.

MOTOROLA

4

High–Speed CMOS Logic Data

DL129 — Rev 6

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