MC54/74HC354
Valid
VCC
D0–D7
50%
A0–A2
GND
Data–Latch
tsu
th
VCC
Enable
50%
GND
Figure 5.
DEVICE
UNDER
TEST
TEST
POINT
OUTPUT
CL*
TEST CIRCUITS
DEVICE
UNDER
TEST
TEST
POINT
OUTPUT
1kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ and tPZH.
*Includes all probe and jig capacitance
Figure 6.
*Includes all probe and jig capacitance
Figure 7.
MOTOROLA
6
High–Speed CMOS Logic Data
DL129 — Rev 6