MC145572EVK 데이터 시트보기 (PDF) - Motorola => Freescale
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MC145572EVK Datasheet PDF : 52 Pages
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Freescale Semiconductor, Inc.
LIST OF FIGURES
Paragraph
Number
Title
Figure 1-1. Motorola Silicon Applications and the MC145572EVK . . . . . . . . . . . . . . . . .
Figure 1-2. MC145572EVK Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1-3. MC145572EVK DIP Switch Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1-4. External Connections to the MC145572EVK . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-1. NT Line Interface Schematic and Component Values . . . . . . . . . . . . . . . . . .
Figure 2-2. LT Line Interface Schematic and Component Values . . . . . . . . . . . . . . . . . .
Figure 2-3. EIA-232 Interface Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-4. Access to Bit Error Analyzer Interface Through J22 and J9 Headers . . . . . .
Figure 2-5. BERT Gated Clock Ñ 8-Bit Gated Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-6. BERT Gated Clock Ñ 10-Bit Gated Clock . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-7. Bit Error Rate Test Set-Up NT Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-8. Loop-Back Modes for the MC145572EVK . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-9. Power Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MOTOROLA
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MC145572EVK
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